Date   : Wed, 14 Jul 1993 10:17:23 +0100 (BST)
From   : "I Stephenson" <ian@...>
Subject: Re: Tube connections (was RE: colour Graphics) 

>Hmmm, but does the tube ULA mask out the illegal address?

possibly possibly not, but your best bet is to mask out the extra addresses in  
your board, then attach the 2P to that. This will probably be necessary anyway,  
as the tube is sensitive about what loads it can drive. If you add a buffer  
then you an exted the length of the cable, and I would sugguest passing through  
NTUBE only for addresses in the range E0->EF, keeping F0->FF for yourself.

>But what about the other direction? Are the tube registers polled on the IO
>processor? I always assumed that they were tested on IRQ, in fact, it
>seems strange that Tube IRQ is an output, as the IRQ line is used for all
>the hardware that the 2nd P shouldn't care about. Are you sure about that??

There are no references to IRQ's or NMI's on the circuit diagram that I have.  
Though its possible that they've been missed out (unlikely), it makes sense to  
have NO interupt connections accross the systems.

Any interupts on the 2P should be generated by hardware on that machine -  
otherwise what is it going to service! No doubt certain writes to the tube chip  
DO generate interupts, but these are strictly internal.

The Host can operate via polling, as its not actually DOing anything else. The  
timing isn't critical (for most comms), as the tube chip ios designed to allow  
the systems to run asyncchronously. Using interupts would lock the two machines  
together, and drastically reduce performance (self timed systems are currently  
hot research, as they're difficult to build, but invariably run much faster, as  
each part runs flat ot whenever it can).

Ian