Date   : Tue, 28 Nov 1995 14:22:05 GMT
From   : Angus Duggan <angus@...>
Subject: 65c02 instructions

James Fidell writes:
>Can anyone tell me what the extra instructions in the 65c02 instruction
>set do ?  What I'd really appreciate is an explanation of what each
>instruction does, how it affects the status register flags and the number
>of cycles it takes to complete, but right now I'd just settle for
>an explanation of what TSB, RMB, TRB, BBR, SMB and BBS do.

TSB and TRB are test and set bit/test and reset bit. They have zero page and
absolute modes, and AFAIR they test accumulator against memory and set/reset
the bits in the memory. I believe the test result is in Z.

SMB0..SMB7 are set memory bit; they reset a bit in zp without affecting the
registers.

RMB0..RMB7 are reset memory bit; they reset a bit in zp without affecting the
registers.

BBS0..BBS7 are branch if bit set; they test a ZP location and then branch on
the result.

BBR0..BBR7 are branch if bit set; they test a ZP location and then branch on
the result.

There are also JMP (ab,X), PHX, PHY, PLX, PLY (yay!), and STZ (store zero)
instructions.

a.
--
Angus Duggan, Harlequin Ltd., Barrington Hall, | INET: angus@...            
Barrington, Cambridge CB2 5RG, U.K.            | PHONE: +44(0)1223 873838