Date   : Thu, 07 Feb 2002 14:43:15 GMT
From   : Thomas Harte <thomasharte@...>
Subject: Re[1]: Re[1]: Firetrack

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[cut : disproof of 'count up to R5 after vsync' theory]
> Any more thoughts?

Purely since no-one else seemed likely to, I've posted a 
question on comp.sys.amstrad.8bit where everyone seems to 
know everything, which no doubt will yield some clues. 

In the mean, I must admit I seem to have heinously misread 
the documentation to come up with that theory. So the smart 
thing to do is to cut me out of the loop and directly present the 
best quote in any documentation I can find :

"This 5 bit register is compared against a scan line counter 
started at some point in the Vertical Control loop (just before a 
new screen, or at the end of the previous VC loop, it's the 
same)."

Which seems to suggest either it is done when the vertical 
character line count hits vertical total or when it is zero'd. 
However I don't see how these are 'the same' with respect to 
when you'd want to reload the register.

-Thomas
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