Date   : Sat, 28 Feb 2004 11:14:03 +0100 (GMT)
From   : Johan Heuseveldt <johan@...>
Subject: Re: IDE Interface for BBC

Hi all,

On Tue 24 Feb, Johan Heuseveldt wrote:
> On Mon 23 Feb, Jonathan Graham Harston wrote:
> 
> > I've updated the circuit diagram at
> > http://www.mdfs.net/Info/Comp/BBC/Hardware/IDE/8bitcd.gif

[snip]

> Hm, I checked my own story, and indeed I seem to have a bad day then.

As you all have noticed, I had had some difficulties in expressing my ideas
and views regarding logic for address decoding, including the read and write
strobes.

As a drawing can say more than a thousands words, I made a small drawing, and
want to put it on my site. Accessing my homepage was a bit difficult the last
few days, but yesterday it seems ok again. It's ready for down load:

  <http://www.waarland.demon.nl/draw.zip>

Please note it's for the idea, what to syncronise or not. The actual
inplementation just depends what glue logic the designer has left, and wants
to use. I only want to show you the principles I have in mind.

> Look at the 8271 (as Sprow suggested), and note that CS is not synchronized
> to whatever clock or timing signal, and is dirty as ever can be: all
> glitches during address stabilisation are NOT suppressed!

A single 138 (74xx(x) family) is enough to create both CS signals.

[snip]

>  2: In principle the RD and WR strobe are ok.
> [...]
> I don't know. So in case of any doubt, synchronise with the 1MHz bus
> signal, and you can be sure that a simultanous glitch/occurence of CS with
> RD/WR in the same clock phase will never happen, during synchronising the
> 2MHz clock (stretched 1rst phase) to the 1MHz clock (fixed timings). [...]

I gave that some more thoughts, and looked at the circuit of the 8271.
Of course, how could I forget! A synchronisation /is/ necessary because
glitches on nRD and nWR are /not/ allowed on these during clock phase 1.
That's why it should be synchronised.

Two circuits are there, including one with a 139 and a standard one with
three 2-input NAND gates. And of course you can use the clean up circuit 2
as well. Not number 1 clean up circuit, as this is asserted during clock
phase 1 too.

So I hope the drawings are much better than I've ever stumbled before.

In general: address set up during clock phase 1
            actual access with RD or WR during clock phase 2


greetings,
johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
In a fight between you and the world, back the world.
Franz Kafka