Date   : Wed, 08 Aug 2007 00:14:34 +0100
From   : jgh@... (Jonathan Graham Harston)
Subject: Emulating Econet hardware?

>Message-ID: <d8834d20708061250y337ef241x892e1f06a9db74ec@...>
 
"Alex Taylor" <zeem.uk@...> wrote:
> I was originally wondering if it was possible to make a simple
> parallel-to-DIN cable and emulate the whole thing in software, like
 
In software? Eeek! It's exactly the sort of task existing hardware
is so much more effective in doing.
 
A bidirectional parallel port had 8 data lines, four output
control lines and four input control lines. To interface to the
standard Econet module you need 8 data lines, four output control
lines and an interupt input line. It's physically interfacable:
 
      25-D
    Parallel               Econet
     Port                  Module
    
      D7   ------<->-------  D7
      D6   ------<->-------  D6
      D5   ------<->-------  D5
      D4   ------<->-------  D4
      D3   ------<->-------  D3
      D2   ------<->-------  D2
      D1   ------<->-------  D1
      D0   ------<->-------  D0
    
    STROBE ------>---------  RS0
    AUTOFD ------>---------  RS1
    INIT   ------>---------  RST
    SLCTIN ------>---------  R/W
    
    ACK    ------<---------  IRQ
    BUSY   ------<----
    PE     ------<----
    ERROR  ------<----
 
You would need to find a +5v line. As Econet is a background
interupt device, you would need to find a way of getting a signal
from the parallel port to generate an interupt. I don't known PC
hardware in enough detail, but on the BBC the ACK line is
connectsed to the USER VIA CA1, and can trigger IRQs.
 
As has been pointed out, interupt latency is the limiting factor,
but most PCs nowadays run faster than the 2MHz BBC which managed
to grab incoming data adequately. However, PCs are notoriously
crap dealing with background interupt processing.
 
With a network clock running at 200KHz, up to 25,000 bytes fly past
every second. Each byte needs to be removed from the ADLC within 40us. 
The 2MHz 6502 has 80 clock cycles available in that 40us time-slice.
A 200MHz 80x86 would have 8000 cycles to pull a byte from the ALDC
before it was trampled by the next byte.
 
It would all depend on
 
- the parallel port being able to be programmed to raise interupts
- the parallel port being able to be 'turned around' in less than 20us
- the operating system allowing you to access the hardware and memory
  directly
 
-- 
J.G.Harston - jgh@...                - mdfs.net/User/JGH
Taxation is like dairy farming. You have to extract the maximum
amount of milk with the minimum amount of moo.