Date   : Fri, 02 Nov 2012 09:59:39 -0500
From   : jules.richardson99@... (Jules Richardson)
Subject: 6502 timing and zero-page instructions

Does anyone know how many cycles it takes for a zero-page AND or ORA 
instruction to complete on the 6502?

The opcode list at http://www.6502.org/tutorials/6502opcodes.html for the 
NMOS CPU says two, but I'm not sure how - the timing diagrams seem to say 
that it needs almost a full cycle to get valid data on the data bus during 
a read, and so surely three cycles are needed:

   c1: opcode fetch,
   c2: operand fetch,
   c3: data fetch from location [0,operand] (followed by logical op
       within the same cycle)

Some resources on the 'net do say it's three (as is the minimum for all 
other ZP instructions), but there seem to be a similar number of sites out 
there that say two.

cheers

Jules