ARM Instruction Encoding

 31-28  27 26  25  24 23 22 21  20    19-16     15-12   11-8  7-4  3-0
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| cond | 0  0 | 0 | 0  0  0  0 | S |   op1   |   dest  | src |1001|op2 |   MUL          ARM2+
| cond | 0  0 | 0 | 0  0  0  1 | S |   op1   |   dest  | src |1001|op2 |   MLA          ARM2+
| cond | 0  0 | 0 | 1  0  0  1 | 0 | <--------value--------> |0111|val |   BKPT
| cond | 0  0 | 0 | 1  0  B  0 | 0 |  source |   dest  | 0000 1001 op1 |   SWP[B]       ARM3+
| cond | 0  0 | 0 | 1  0  R  0 | 0 | 1 1 1 1 |   dest  | 0000 0000 0000|   MRS Rn,[C|S]PSR
| cond | 0  0 | 0 | 1  0  R  1 | 0 | bitmask | 1 1 1 1 | 0000 0000 src |   MSR [C|S]PSR_type,Rn
| cond | 0  0 | 1 | 1  0  R  1 | 0 | bitmask | 1 1 1 1 |  rotate  |val |   MSR [C|S]PSR_type,#imm
| cond | 0  0 | I | 0  0  0  0 | S |   op1   |   dest  |   addr_mode   |   AND          ARM1+
| cond | 0  0 | I | 0  0  0  1 | S |   op1   |   dest  |   addr_mode   |   EOR          ARM1+
| cond | 0  0 | I | 0  0  1  0 | S |   op1   |   dest  |   addr_mode   |   SUB          ARM1+
| cond | 0  0 | I | 0  0  1  1 | S |   op1   |   dest  |   addr_mode   |   RSB          ARM1+
| cond | 0  0 | I | 0  1  0  0 | S |   op1   |   dest  |   addr_mode   |   ADD          ARM1+
| cond | 0  0 | I | 0  1  0  1 | S |   op1   |   dest  |   addr_mode   |   ADC          ARM1+
| cond | 0  0 | I | 0  1  1  0 | S |   op1   |   dest  |   addr_mode   |   SBC          ARM1+
| cond | 0  0 | I | 0  1  1  1 | S |   op1   |   dest  |   addr_mode   |   RSC          ARM1+
| cond | 0  0 | I | 1  0  0  0 | 1 |   op1   | 0 0 0 0 |   addr_mode   |   TST          ARM1+
| cond | 0  0 | I | 1  0  0  1 | 1 |   op1   | 0 0 0 0 |   addr_mode   |   TEQ          ARM1+
| cond | 0  0 | I | 1  0  1  0 | 1 |   op1   | 0 0 0 0 |   addr_mode   |   CMP          ARM1+
| cond | 0  0 | I | 1  0  1  1 | 1 |   op1   | 0 0 0 0 |   addr_mode   |   CMN          ARM1+
| cond | 0  0 | I | 1  1  0  0 | S |   op1   |   dest  |   addr_mode   |   ORR          ARM1+
| cond | 0  0 | I | 1  1  0  1 | S | 0 0 0 0 |   dest  |   addr_mode   |   MOV          ARM1+
| cond | 0  0 | I | 1  1  1  0 | S |   op1   |   dest  |   addr_mode   |   BIC          ARM1+
| cond | 0  0 | I | 1  1  1  1 | S | 0 0 0 0 |   dest  |   addr_mode   |   MVN          ARM1+
| cond | 0  1 | I | P  U  B  W | 0 | basereg |    op1  |   addr_mode   |   STR[B]       ARM1+
| cond | 0  1 | I | P  U  B  W | 1 | basereg |   dest  |   addr_mode   |   LDR[B]       ARM1+
| cond | 1  0 | 0 | P  U  S  W | 0 | basereg |  <-----reg list----->   |   STM          ARM1+
| cond | 1  0 | 0 | P  U  S  W | 1 | basereg |  <-----reg list----->   |   LDM          ARM1+
| cond | 1  0 | 1 | L | <-------------------target------------------>  |   B/BL         ARM1+
| cond | 1  1 | 0 | 0 |x x x x x x x x x x x x x x x x x x x x x x x x |                ARM1+
| cond | 1  1 | 0 | 1 |x x x x x x x x x x x x x x x x x x x x x x x x |                ARM1+
| cond | 1  1 | 1 | 0 |x x x x x x x x x x x x x x x x x x x x x x x x |                ARM1+
| cond | 1  1 | 1 | 1 | <-------------------value------------------->  |   SWI          ARM1+
-----------------------------------------------------------------------------------------------

Notes
-----
bitmask: byte of PSR to modify: b16: PSR_c b0-b7 control field
                                b17: PSR_x b8-b15 extension field
                                b18: PSR_s b16-b23 status field
                                b19: PSR_f b24-b31 flags field