8251 UART
                                =========

+--------+----------------------------+-----------------------------+
|        |      Write                 |         Read                |
+========+============================+=============================+
| base+0 |   Transmit Data Register   |    Receive Data Register    |
+--------+----------------------------+-----------------------------+
| base+1 |      Control Register      |       Status Register       |
|        |  b7: Enter Hunt Mode       |  b7: Data Set Ready         |
|        |  b6: Reset, next is Mode   |  b6: SYNC/BREAK Detected    |
|        |  b5: Request To Send       |  b5: Framing Error          |
|        |  b4: Reset Errors          |  b4: Data Overrun           |
|        |  b3: Send Break            |  b3: Parity Error           |
|        |  b2: Receive Enable        |  b2: Transmit Empty         |
|        |  b1: Data Terminal Ready   |  b1: Receive Ready          |
|        |  b0: Transmit Enable       |  b0: Transmit Ready         |
|        |                            |                             |
|        | Mode Register (after Reset)|                             |
|        |  b7-6: Stop bits           |                             |
|        |  b5: Odd/Even Parity       |                             |
|        |  b4: Enable Parity         |                             |
|        |  b3-2: Word Length         |                             |
|        |  b1-0: Clock Divide        |                             |
+--------+----------------------------+-----------------------------+