LDA A ADD B STR BThe PDP-11 instruction set also contains a full set of conditional branches that eliminate excessive use of jump instructions. PDP-11 instructions fall into one of seven categoreis:
||COM(B)||1's complement dst
||NEG(B)||2's complement negate dst
||TSTSET||test dst, set low bit (MICRO/J-11 only)
||WRTLCK||read/lock dst, write/unlock R0|
into dst (MICRO/J-11 only)
|Shift & Rotate
||ASR(B)||arithmetic shift right
||ASL(B)||arithmetic shift left
||MOV(B)||move source to destination
||ADD||add source to destination
||SUB||subtract source from destination
||CMP(B)||compare source to destination
||ASHC||arithmetic shift combined
The format of most double-operand instructions, though similar to that of single-operand instructions, has two fields for locating operands. One field is called the source field, the other is called the destination field. Each field is further divided into addressing mode and selected register. Each field is completely independent. The mode and register used by one field may be completely different than the mode and register used by another field.
Byte instructions are specified by setting bit 15. Thus, in the case of the MOV instruction, bit 15 is 0; whin bit 15 is set, the mnemonic is MOVB. There are no byte operations for ADD and SUB, i.e., no ADDB or SUBB.
||BNE||branch if not equal (to zero)
||BEQ||branch if equal (to zero)
||BPL||branch if plus
||BMI||branch if minus
||BVC||branch if overflow is clear
||BVS||branch if overflow is set
||BCC||branch if carry is clear
||BCS||branch if carry is set
||Signed Conditional Branch
||BGE||branch if greater than or equal (to zero)
||BLT||branch if less than (zero)
||BGT||branch if greater than (zero)
||BLE||branch if less than or equal (to zero)
||SOB||subtract one and branch (if not = 0)
||Unsigned Conditional Branch
||BHI||branch if higher
||BLOS||branch if lower to same
||BHIS||branch if higher or same
||BLO||branch if lower
||JSR||jump to subroutine
||RTS||return from subroutine
||MARK||facilitates stack clean-up procedures
JSR Instruction Format
RTS Instruction Format
The RTS (return from subroutine) instruction uses the link to return control to the main program once the subroutine is finished.
||CSM||call to supervisor mode
||RTI||return from interrupt
||RTT||return from interrupt
The three ways to leave a main program are:
||WAIT||wait for interrupt
||MTPD||move to previous data space
||MTPI||move to previous instruction space
||MFPD||move from previous instruction space
||MFPI||move from previous instruction space
||MTPS||move byte to processor status word
||MFPS||move byte from processor status word
||MFPT||move from processor type
Note that on the PDP-11/70, the four instructions for referencing the previous address space (MTPD, MTPI, MFPD, MFPI) use the General Register set indicated by PSW<11> when they are executed.
||CLC, CLV, CLZ, CLN, CCC||clear
||SEC, SEV, SEZ, SEN, SCC||set
The four condition code bits are:
Z bit - Whenever the CPU sees that the result of an instruction is zero, it sets the Z bit. If the result is not zero, it clears the Z bit. There are a number of ways of obtaining a zero result:
C bit - The CPU sets the C bit automatically when the result of an instruction has caused a carry out of the most significant bit of the result. Otherwise, the C bit is cleared. During rotate instructions (ROL and ROR), the C bit forms a buffer between the most significant bit and the least significant bit of the word. A carry of 1 sets the C bit while a carry of 0 clears the C bit. However, there are exceptions. For example:
One way is for the CPU to test for a change of sign.
The format of the condition code operators is:
Single-Operand Instruction Example
This routine uses a tally to control a loop, which clears out a specific block of memory. The routine has been set up to clear 30(base 8) byte locatations beginning at memory address 600.
|INIT:||MOV #600, R0|
MOV #30, R1
Double-Operand Instruction Example
This routine moves characters to be printed from location 600 into a print buffer area in memory.
|INIT||MOV #600, R0||; set up source address|
|MOV #prtbuf, R1||; set up destination address|
|MOV #76, R2||; set up loop count|
|START||MOVB (R0)+, (R1)+||; move one character|
|; and increment|
|; both source and|
|; destination addresses|
|DEC R2||; decrement count by one|
|BNE START||; loop back if|
|HALT||decremented counter is not|
|; equal to zero|
Branch Instruction Example
NOTE: branch instruction offsets are limited to the range of +177(base 8) to -200(base 8) words.
A payroll program has set up a series of words to identify each employee by his badge number. The high byte of the word contains the employee's badge number, the low byte contains an octal number ranging from 0 to 13 which represents his salary. These numbers represent steps within three wage classes to identify which employees are paid weekly, monthly, or quarterly. It is time to make out weekly paychecks. Unfortuneately, employee information has been stored in a random order. The problem is to extract the names of only those employees who receive a weekly paycheck. Employee payroll numbers are assigned as follows: 0 to 3 - Wage Class I (weekly), 4 to 7 - Wage Class II (monthly), 10 to 13 - Wage class III (quarterly).
600 is the starting address of memory block containing the employee payroll information. 1264 is the final address of this data area. The following program searches through the data area and finds all numbers representing Wage Class I, and, each time an appropriate number is found, stores the employee's badge number (just the high byte) on a Last-in/First-out stack which begins at location 4000.
|INIT||MOV #600, R0|
|MOV #4000, R1|
|STACK||MOVB (R0), -(R1)|
|CMP #1264, R0|
Available on MICRO/J-11 and PDP-11/44 only.
MFPD, MFPI, MTPD, MTPI
Available on the MICRO/J-11, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, PDP-11/24, PDP-11/44, and VAX-11 compatibility mode.
Available on the MICRO/T-11, MICRO/J-11, LSI-11/2, FALCON SBC-11/21, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, and PADP-11/24.
Available on the MICRO/T-11, MICRO/J-11, FALCON SBC-11/21, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, PDP-11/24, and PDP-11/44.
Available on MICRO/J-11 and PDP-1/44 only.
Available on MICRO/J-11 only.
Extended Integer Instructions (EIS)
EIS is standard on:
Floating Instruction set (FIS)
FIS is unique to:
Don S. Bidulock