Department of Computer Science

PDP-11 Processor Handbook

Instruction Set


Introduction

The PDP-11 instruction set offers a wide selection of operations and addressing modes. To save memory space and to simplify the implementation of control and communications applications, the PDP-11 instructions allow byte and word addressing in both single- and double-operand formats. By using the double-operand instructions, you can perform several operations with a single instruction. For example, ADD A,B adds the contents of location A to location B, storing the result in location B. Traditional computers would implement this instruction this way:
              LDA A
              ADD B
              STR B
The PDP-11 instruction set also contains a full set of conditional branches that eliminate excessive use of jump instructions. PDP-11 instructions fall into one of seven categoreis:

Single-Operand Instructions

MnemonicInstruction
General
CLR(B)clear destination
COM(B)1's complement dst
INC(B)increment dst
DEC(B)decrement dst
NEG(B)2's complement negate dst
NOPno operation
TST(B)test dst
TSTSETtest dst, set low bit (MICRO/J-11 only)
WRTLCKread/lock dst, write/unlock R0
into dst (MICRO/J-11 only)
Shift & Rotate
ASR(B)arithmetic shift right
ASL(B)arithmetic shift left
ROR(B)rotate right
ROL(B)rotate left
SWABswap bytes
Multiple Precision
ADC(B)add carry
SBC(B)subtract carry
SXTsign extend

Instruction Format

Single-Operand Instruction Format

Double-Operand Instructions

MnemonicInstruction
General
MOV(B)move source to destination
ADDadd source to destination
SUBsubtract source from destination
CMP(B)compare source to destination
ASHshift arithmetically
ASHCarithmetic shift combined
MULmultiply
DIVdivide
Logical
BIT(B)bit test
BIC(B)bit clear
BIS(B)bit set
XORexclusive OR

Instruction Format

Double-Operand Instruction Format

The format of most double-operand instructions, though similar to that of single-operand instructions, has two fields for locating operands. One field is called the source field, the other is called the destination field. Each field is further divided into addressing mode and selected register. Each field is completely independent. The mode and register used by one field may be completely different than the mode and register used by another field.

Byte Instructions

The PDP-11 includes a full complement of instructions that manipulate byte operands. Since all PDP-11 addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified register to be modified by one to point to the next byte of data. Byte operations in register mode access the low-order byte of the specified register. These provisions enable the PDP-11 to perform as either a word or byte processor. The numbering scheme for word and byte addresses in memory is:

Byte instructions are specified by setting bit 15. Thus, in the case of the MOV instruction, bit 15 is 0; whin bit 15 is set, the mnemonic is MOVB. There are no byte operations for ADD and SUB, i.e., no ADDB or SUBB.

Example:

SymbolicOctal
CLR0050DDClear Word
CLRB1050DDClear Byte

Branch Instructions

MnemonicInstruction
Branch
BRbranch (unconditional)
BNEbranch if not equal (to zero)
BEQbranch if equal (to zero)
BPLbranch if plus
BMIbranch if minus
BVCbranch if overflow is clear
BVSbranch if overflow is set
BCCbranch if carry is clear
BCSbranch if carry is set
Signed Conditional Branch
BGEbranch if greater than or equal (to zero)
BLTbranch if less than (zero)
BGTbranch if greater than (zero)
BLEbranch if less than or equal (to zero)
SOBsubtract one and branch (if not = 0)
Unsigned Conditional Branch
BHIbranch if higher
BLOSbranch if lower to same
BHISbranch if higher or same
BLObranch if lower

Instruction Format

Jump and Subroutine Instructions

MnemonicInstruction
JMPjump
JSRjump to subroutine
RTSreturn from subroutine
MARKfacilitates stack clean-up procedures

JSR Instruction Format

RTS Instruction Format

RTS Instruction Format

The RTS (return from subroutine) instruction uses the link to return control to the main program once the subroutine is finished.

Traps and Interrupts

MnemonicInstruction
EMTemulator trap
TRAPtrap
BPTbreakpoint trap
IOTinput/output trap
CSMcall to supervisor mode
RTIreturn from interrupt
RTTreturn from interrupt

The three ways to leave a main program are:

In each case, a jump to another program occurs. Once the latter program has been executed, control is returned to the proper point in the main program.

Miscellaneous Instructions

MnemonicInstruction
HALThalt
WAITwait for interrupt
RESETreset UNIBUS
MTPDmove to previous data space
MTPImove to previous instruction space
MFPDmove from previous instruction space
MFPImove from previous instruction space
MTPSmove byte to processor status word
MFPSmove byte from processor status word
MFPTmove from processor type

Note that on the PDP-11/70, the four instructions for referencing the previous address space (MTPD, MTPI, MFPD, MFPI) use the General Register set indicated by PSW<11> when they are executed.

Condition Code Operation

MnemonicInstruction
CLC, CLV, CLZ, CLN, CCCclear
SEC, SEV, SEZ, SEN, SCCset

The four condition code bits are:

These four bits are part of the processor status word (PS). The result of any singal-operand or double-operand instruction affects one or more of the four condition code bits. A new set of condition codes is usually created after execution of each instruction. Some condition codes are not affected by the execution of certain instructions. The CPU may be asked to check the condition codes after execution of an instruction. The condition codes are used by the vairous instructions to check software conditions.

Z bit - Whenever the CPU sees that the result of an instruction is zero, it sets the Z bit. If the result is not zero, it clears the Z bit. There are a number of ways of obtaining a zero result:

N bit - The CPU looks only at the sign bit of the result. If the sign bit is set, indicating a negative value, the CPU sets the N bit. If the sign bit is clear, indicating a positive value, the the CPU clears the N bit.

C bit - The CPU sets the C bit automatically when the result of an instruction has caused a carry out of the most significant bit of the result. Otherwise, the C bit is cleared. During rotate instructions (ROL and ROR), the C bit forms a buffer between the most significant bit and the least significant bit of the word. A carry of 1 sets the C bit while a carry of 0 clears the C bit. However, there are exceptions. For example:

V bit - The V bit is set to indicate that an overflow condition exists. An overflow means that the result of an instruction is too large to be placed in the destination. The harware uses one of two methods to check for an overflow condition.

One way is for the CPU to test for a change of sign.

Another method used by the CPU is to test the N bit and C bit when dealing with shift and rotate instructions. More than one condition code can be set by a particular instruction. For example, both a carry and an overflow condition may exist after instruction execution.

Instruction Format

Condition Code Operators' Format

The format of the condition code operators is:

Examples

The following examples and explanations illustrate the use of the various types of instructions in a program.

Single-Operand Instruction Example

This routine uses a tally to control a loop, which clears out a specific block of memory. The routine has been set up to clear 30(base 8) byte locatations beginning at memory address 600.
INIT:MOV #600, R0
MOV #30, R1
LOOP:CLRB (R0)+
DEC R1
BNE LOOP
HALT
Program Description:

Double-Operand Instruction Example

This routine moves characters to be printed from location 600 into a print buffer area in memory.
INITMOV #600, R0; set up source address
MOV #prtbuf, R1; set up destination address
MOV #76, R2; set up loop count
STARTMOVB (R0)+, (R1)+; move one character
; and increment
; both source and
; destination addresses
DEC R2; decrement count by one
BNE START; loop back if
HALTdecremented counter is not
; equal to zero
Program Description:

Branch Instruction Example

NOTE: branch instruction offsets are limited to the range of +177(base 8) to -200(base 8) words.

A payroll program has set up a series of words to identify each employee by his badge number. The high byte of the word contains the employee's badge number, the low byte contains an octal number ranging from 0 to 13 which represents his salary. These numbers represent steps within three wage classes to identify which employees are paid weekly, monthly, or quarterly. It is time to make out weekly paychecks. Unfortuneately, employee information has been stored in a random order. The problem is to extract the names of only those employees who receive a weekly paycheck. Employee payroll numbers are assigned as follows: 0 to 3 - Wage Class I (weekly), 4 to 7 - Wage Class II (monthly), 10 to 13 - Wage class III (quarterly).

600 is the starting address of memory block containing the employee payroll information. 1264 is the final address of this data area. The following program searches through the data area and finds all numbers representing Wage Class I, and, each time an appropriate number is found, stores the employee's badge number (just the high byte) on a Last-in/First-out stack which begins at location 4000.

INITMOV #600, R0
MOV #4000, R1
STARTCMPB(R0), #3
BHI CONT
STACKMOVB (R0), -(R1)
CONTINC R0
CMP #1264, R0
BHIS START

Program Description:

Summary of PDP-11 Instruction Set

Basic PDP-11 Instruction Set
ADCBITCOMROL
ADCBBITBCOMBROLB
ADDBLEDECROR
ASLBLODECBRORB
ASLBBLOSEMTRTI
ASRBLTHALTRTS
ASRBBMIINCRTT
BCCBNEINCBSBC
BCSBPLIOTSBCB
BEQBPTJMPSCC,SEN,
SEZ,
SEV,SEC
BGEBRJSRSOB
BGTBVCMARKSUB
BHIBVSMOVSXT
BHISCLRMOVBSWAB
BICCLRBNEGTRAP
BICBCCC, CLNNEGBBTST
CLZ,
CLV, CLC
BISCMPNOPTSTB
BISBCMPBRESETXOR
WAIT
The basic PDP-11 instructions are standard on: The PDP-11 compatibility mode on VAX-11 implements all basic PDP-11 instructions except: MARK, RESET, TRAP, WAIT, BPT, EMT, IOT, and HALT.

CSM
Available on MICRO/J-11 and PDP-11/44 only.

MFPD, MFPI, MTPD, MTPI
Available on the MICRO/J-11, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, PDP-11/24, PDP-11/44, and VAX-11 compatibility mode.

MFPS, MTPS
Available on the MICRO/T-11, MICRO/J-11, LSI-11/2, FALCON SBC-11/21, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, and PADP-11/24.

MFPT
Available on the MICRO/T-11, MICRO/J-11, FALCON SBC-11/21, LSI-11/23, MICRO/PDP-11, PDP-11/23-PLUS, PDP-11/24, and PDP-11/44.

SPL
Available on MICRO/J-11 and PDP-1/44 only.

TSTSET, WRTLCK
Available on MICRO/J-11 only.

Extended Integer Instructions (EIS)
ASH
ASHC
DIV
MUL

EIS is standard on:

EIS is also available as an option on the LSI-11/2

Floating Instruction set (FIS)
FADD
FSUB
FMUL
FDIV

FIS is unique to:


Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

University of Calgary