Simple 6809 Tube CoProcessor Design
           -----------------------------------

I recommend the following design, based on the 6502 CoPro which
is a R/W memory-mapped CPU, instead of a RD/WR IO-mapped CPU:
 
   +--------+     +------+    +-----+            +------+
   |      D0|=====| 64K  |====|  4K |============| Tube |
   | 6809 ..|     | SRAM |    | ROM |            | ULA  |
   |      D7|=====|      |====|     |============|      |
   |        |     |      |    |     |            |      |
   |      A0|=====|A0    |====|A0   |============|PA0   |
   |      ..|     |      |    |..   |            |..    |
   |     A15|=====|A15   |====|A11  |============|PA2   |
   |        |     |      |    +-----+            |      |
   |     W/R|-----|W/R   |-----+---------+---\   |      |
   |        |     +------+     |         |NAND>--|PRD   |
   |       E|--------------+---|---------+---/   |      |
   |        |              |   |  +--\           |      |
   |        |              |   +--|NOT>--+---\   |      |
   |        |              |      +--/   |NAND>--|PWR   |
   |        |              +-------------+---/   |      |
   |     NMI|-----+5v                            |      |
   |     IRQ|------------------------------------|PNMI  |
   |    FIRQ|------------------------------------|PIRQ  |
   |     RST|------------------------------------|PRST  |
   |        |                                    |      |
   |        |   +----+                           |      |
   |      BA|---|    |                           |      |
   |      BS|---|    |----+---\                  |      |
   |        |   +----+    |XOR >---A8            |      |
   |      A8|-------------+---/                  |      |
   |        |                                    |      |
                                                 |      |
  A15---------+-----\                            |      |
   ..---------+      |                           |      |
   A3---------+      |                           |      |
       +--\   |      |                           |      |
   A4--|NOT>--+13-NAND>----+---------------------|PCS   |
       +--/   |      |     |  +--\   +------+    +------+
       +--\   |      |     ---|NOT>--|RESET |--->RAM CS
   A8--|NOT>--+-----/         +--/   |TOGGLE|--->ROM CS
       +--/                          +------+
  
* BA/BS is decoded so that when vectors are fetched A8 is toggled so
  vectors are fetched from &FEFx instead of &FFFx.

* Address decoded so all access to &FEEx accesses Tube registers.

* All writes (other than the Tube ULA) goes to RAM

* After RESET, all reads (other than the Tube ULA) goes to ROM

* After a Tube ULA access, all reads (other than Tube) goes to RAM

In other words, on RESET, the memory map is filled with reflections of
the ROM. The startup code copies the ROM to RAM by effectively doing
FOR A=&F000 TO &FFFF:?A=?A:NEXT. Any access to the Tube ULA toggles off
ROM access so all further reads come from RAM. Note that this means that
the CPU cannot read from a subroutine stack until the ROM is paged out.
A refinement is to monitor A15 and allow reads from low RAM at RESET.