Date   : Thu, 28 Aug 1997 01:35:32 GMT
From   : adq@... (Andrew de Quincey)
Subject: Re: Sideways RAMs

On Wed, 27 Aug 1997 08:33:18 -0700, you wrote:

>Andrew de Quincey writes:
>>
>>Hi again,
>>
>>Another problem: 
>>
>>I was under the impression that the sideways RAM for the BBC were
>>Static RAM chips plugged into one of the ROM sockets.....
>
>Nope. The sockets are for ROMs, which are nearly, but not quite,
compatible
>with 27xxx series ROMs. There is no write enable line on the ROM
sockets.
>
>Not surprising. I can't remember what signal goes to write enable, but
it
>won't be what you expect. You need some extra logic to determine whether
>write enable should be on, and whether the socket your chip is in is the
>correct one to write to. This is why there were sideways RAM boards
(though I
>built one myself initially, ISTR the extra logic was only a couple of
gates).

I think I can see how it works from the circuit diagram.

Write enable is permanently pulled high...

meanwhile: reading from a ROM goes as follows:


1) A line, ROMSEL is pulled low when the system wants to *read* from a
   paged ROM... *only* reading 

  In more detail, ROMSEL is generated from some address decoding logic

  AND the R/W line from the 6502....

  It all comes down to one decoder (IC26), and two bits: one is
  Address line 4, and the other is the R/W signal

current inputs and output to this decoder are:

 INPUTS        OUTPUT
 --------------------  ---------------------------
  A4   R/W=09
  0    0       VIDPROC
  0    1       ROMSEL
  1    0       INTON
  1    1       not connected


2) Then there's a counter (IC76) that takes the 4bits of data on the 
    data bus when ROMSEL is low, and stores it... 
    (the ROM number I assume)


3) ROMSEL is then made high..... 

4) The processor then outputs the address is wants to read/write from

5) Due to this address , and some more address decoding logic, the
   output enable line of the all ROM chips are pulled low (see later)

6) The  counter (IC76)  storing the ROM number (see stage 2) then
   outputs the value through
   a wee decoder (IC20) which generates the relevant Chip Select
   signal..
   This only occurs when both A14 and A15 are high (asserted)

7) Finally, the ROM splurges out the byte of data...


So, what I need to do is generate the Write Enable signal, and fiddle
the ROMSEL signal.


=46irst of all:
Since ROMSEL only works when the ROM is being READ from, I need a new
signal: RAMSEL (tm :-)

So..... theoretically, to generate my hypothetical RAMSEL
signal, All I need to do is attach a wire to the 4th output of the
decoder mentioned in stage 1, and duplicate the counter chip to
generate the Chip Select signal.

In fact, would I need to duplicate the counter? Surely, all I need to
do is have the existing one also read from the data line when RAMSEL
is asserted..... i.e. join the ROMSEL and RAMSEL lines together (i'd
put in some diodes so I don't get data doing strange things to the
outputs of the decoder chip)



=46inally, I need to generate the Write Enable line...

The way things seem to be arranged are that ROMs' output enables are
asserted whenever FRED, JIM, or the ROM area of memory is being
accessed (also an input from somewhere called 2MHZ ???) 

Soooo... I'd need to have a chip in the way which checked whether the
memory area was being accessed, and instead of always asserting output
enable on the chips, asserts Write enable or Output enable, depending
on the status of the R/W line. i.e. take the old output enable signal,
and the R/W signal, and stick them through a couple of NAND gates,
(with inverters where needed), and put the outputs in to the correct
pins on the Sideways RAM socket.

I think this sounds OK (fingers crossed).... does anyone see any
problems or mistakes with it?

I *wish* I had the Advanced BBC user's guide so I could check all this
stuff up myself :(