Date : Fri, 13 Apr 2001 16:17:01 +0100
From : "Richard Gellman" <r.gellman@...>
Subject: Re: BBC CRTC and ACIA
You really should consult documentation on the 6845 CRTC :P
This is (i think) how certain registers affect the display:
R4 is Vertical Total - i.e. the total characters displayed
there are 8 pixels per character, so total scanlines = R4 x 8
R5 (Vertical adjust) is the number of scanlines added to the bottom of the
screen to account for the Field Blanking Interval, i.e. the time that the
TV/monitor is NOT displaying anything because its moving the cathode ray
back to the top left of the screen
Note, that somehow, Modes 3 & 6 add two blank lines to the characters to
make 10 scanlines per character.
As for the ACIA..
Having just added tape support to BeebEm, i can tell you its a fun little
chip...
The BBC Micro seems to use the chip in non-interrupt mode (or at least when
i forced it to use interrupt mode it made the whole thing stop working).
This means it continously checks the status register to determine if any
data is ready.
Bit 7 of the status register determines if the IRQ output is active, and I
think Bit 7 of the control register determines if interrupts are generated
on receiving input.
When a character is received, it is placed in a buffered data register, i.e.
data can be read in while the data register is full.
The Receive Data Register Full bit (Status reg, bit 0) goes high when this
happens.
bit 2 of the status register is DCD (Data carrier detect), in my experience,
this needs to be low during carrier tone (that continuous high tone), during
data reception, and for a small time after the block is received (i.e.
during the interblock carrier).
Then DCD must go high, then low again during interblock carrier, otherwise
the BBC will only read the first block.
A DCD based interrupt is only generated if:
Bit 7 of the status register is set AND
The DCD input has gone high. (i.e. loss of data carrier).
Obviously the DCD line must go high (no carrier) during silence gaps between
programs.
Also, you must emulate the SERPROC (serial processor) chip which controls
data flow between the 6850 ACIA and the serial/cassette ports
This chip is also responsible for generating the serial receive and transmit
clocks.
-- Richard Gellman
www.rickynet.net/beebem
-----Original Message-----
From: owner-bbc-micro@...
[mailto:owner-bbc-micro@...]On Behalf Of Tom Walker
Sent: Friday, April 13, 2001 3:47 PM
To: bbc-micro@...
Subject: [BBC-Micro] BBC CRTC and ACIA
I've got a couple of questions regarding the 6845 CRTC :
1. Do any registers control the total number of scanlines in a frame (ie 312
for PAL, 262 for NTSC)?
2. What is the exact function of R5 (vertical adjust)?
Also, what happens when the ACIA receives data, or a carrier? How does the
BBC use these interrupts for tape input? Also, what or the OSFSC and OSFILE
entry points for the US BBC OS?
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