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Date   : Tue, 05 Feb 2002 21:11:53 GMT
From   : Thomas Harte <thomasharte@...>
Subject: The internal workings of the CRTC

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The following description is summarised by me mostly from a 
document by Pierre Guerrier which used to be on the Unofficial 
Amstrad WWW resource, but doesn't seem to be any more. Of 
course, the actual VDU in most cases will only pay attention to 
horizontal and vertical sync if they appear to be similar to what 
it believes to be true, so the trick to split screens is to force a 
very quick entry and exit of 'vertical sync' at some point in the 
frame. This can of course be used to affect 'pixel scrolling of 
the entire display', but people don't seem to think Firetrack 
used this method.

Of course, I'm sure everyone is aware that the CRTC is the 
same chip used in the VGA graphics adaptor, so you often find 
this sort of information looking at the very old 'how to do 
graphics with Turbo Pascal' sort of documents that still lie in 
some places on the internet. Particularly with reference to split 
screen effects.

The only odd thing is that it doesn't seem to adequately 
explain how Acorn manage to space character lines by two 
pixels in modes 3 & 6, so it may not actually be a complete 
description, unless I'm missing an implication of something.

Horizontal activities :

The horizontal character counter (HC) and horizontal memory 
address (HMA) are incremented with the CRTC clock. When HC 
is equal to the horizontal total (register 0) it is zero'd, and HMA 
is reloaded from the vertical memory address (VMA).

When 0 <= HC < horizontal displayed (register 1), the 
'horizontal display enable' is set, and on pixel lines, pixels 
appear.

When HC = Hsync position, horizontal sync is set and the 
horizontal sync counter (HSC) is zero'd.

While horizontal sync is set, HSC is incremented with the CRTC 
clock. When it is found to be equal to the low four bits of sync 
width (register 3), the horizontal sync signal is reset.

Vertical activities :

There are two scanline-wise quantity counters - vertical 
counter (VC) which counts in character rows and the scanline 
counter (SC) which counts scanlines within character rows. 
There is additionally a 'vertical memory address' (VMA).

When vertical activities are enabled, SC is incremented when 
horizontal sync is reset. If it is found to be equal to maximum 
raster address (register 9) it is zero'd, VC is incremented and 
VMA is loaded with 1+(the last HMA when horizontal display 
enable was set).

When VC is equal to register 4 it is zero'd, and HMA is loaded 
from registers 12 and 13.

When 0 <= VC < register 9, the 'vertical display enable' is set.

When VC is found to be equal to vsync position (register 9), 
vertical sync is set, vertical activities are suspended and the 
vertical sync counter (VSC) is zero'd.

In non-motorola CRTC's, while vertical sync is set, the VSC is 
incremented on every horizontal sync and when found to be 
equal to the high four bits of sync width (register 3), vertical 
sync is reset. On Motorola CRTC's, the high four bits of 
register 3 are ignored, and vertical sync is always signalled for 
16 scan lines.

When vertical sync exits, the scanline adjust counter (SAC) is 
zero'd and subsequently incremented every horizontal sync. 
Until it is found to be equal to register 5 (vertical total adjust), 
all vertical activities are resumed.

When and how output occurs :

The display enable line is set only when both 'vertical display 
enable' and 'horizontal display enable' conditions hold. It is 
only then that the video circuits are supposed to produce 
display.

The display for any character is composed from the horizontal 
memory address (HMA) loaded onto address lines 3-15 and 
the current scanline counter (SC) onto address lines 0-2.

The cursor :

The cursor is drawn when cursor address (registers 14 & 15) 
matches horizontal memory address (HMA) and the scanline 
counter (SC) is between cursor start (register 10) and cursor 
end (register 11).

-Thomas
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