Date   : Thu, 29 May 2003 02:37:17 +0200
From   : John Kortink <kortink@...>
Subject: Re: Sideways RAM designs

On Wed, 28 May 2003 21:39:56 +0100, Nick B wrote:

>John Kortink wrote:
>
>[...]
>
>>http://web.inter.nl.net/users/J.Kortink/rewire.txt
>>
>>It does involve a bit of work on the underside of the
>>beeb's PCB.
>>
>>[...]
>>
>Thanks John, that looks most interesting. I realised that is quite 
>straightforward to fit SRAM chips to EPROM sockets, it was just deciding
 
>where to get a R/W signal from and how to do the loading & bankswitching
 
>stuff.

The LDA &FE30 by the way, is an error. ROMSEL is write only,
so it should be LDA &F4 (the OS copy) instead. To be safe for
interrupt handlers that access sideways ROM(s), it should be
something like :

DIM Code% 256
P%=Code%
[
 SEI
 LDX &F4
 LDA &83
 STA &FE30
 LDA &82
 LDY #0
 STA (&80),Y
 STX &FE30
 CLI
 RTS
]

Now I'm at it : to load blocks, it's similar, but then better
not disable interrupts during the block copy and explicitly
update the ROMSEL copy before and after, i.e. something like :

DIM Code% 256
P%=Code%
[
 LDA &F4
 PHA
 LDA &83
 SEI
 STA &F4
 STA &FE30
 CLI
 <copy block>
 PLA
 SEI
 STA &F4
 STA &FE30
 CLI
 RTS
]

There are probably utils around to do something *Load-like,
but steer clear from the Solidisk utils you may find because
on Solidisk contraptions, IIRC, the RAM bank that accepts
writes is selected by a seperate latch (in order for the
standard *Load command (and OSFILE 255) to work, pretty
smart really).


John Kortink