Date : Fri, 16 Jan 2004 01:13:31 +0000
From : jgh@... (Jonathan Graham Harston)
Subject: Re: IDE Interface for BBC
jgh@... (Jonathan Graham Harston) wrote:
> Anyway, it passes electrical tests, and appears in the memory map. Now to
> try and actually tansfer some data!
Well, on reading it responds correctly, but try as I might, I can't get it
to respond to commands. I've put a test program at
http://www.mdfs.net/Info/Comp/BBC/Hardware/IDE
On reading the ports, it gives the expected results:
DA ER NM SE CYLIN HD CM
00FC40 00 00 FF FF FF FF FF 00 ........
Status=ok, error=none
On writing, IDEstatus keeps returning &D0, &D1, &50 or &51, ie:
7 BUSY 1 1 0 0
6 READY 1 1 1 1
5 FAULT 0 0 0 0
4 SEEKOK 1 1 1 1
3 DATARQ 0 0 0 0
2 CORRECT 0 0 0 0
1 INDEX 0 0 0 0
0 ERROR 0 1 0 1
ie, there's never any data present.
Checking data sheets in more detail, the T13 specifications say that WR
should be asserted thus:
______________ _________________
ADDR \ /
VALID \______________________________/
_____________________________ _____________
WR \ /
\___________________/
_______________
DATA ____________________/ \____________________________
\_______________/
But the 1MHz bus asserts WR as:
______________ ______________________________
WR \ /
\_______________/
I think I need to somehow push the WR signal along to assert from the
middle of the valid data.
In Ruud Baltisson's interface at http://home.hccnet.nl/g.baltissen/ide.htm
for the C64 the IORD line is delayed through an R/C network, but not the
IOWR line. I'm looking to see if I can something like that.
--
J.G.Harston (JGH BBC PD Library) 70 Camm Street, Walkley, SHEFFIELD S6 3TR
jgh@... - Running on BBCs & Masters with SJ MDFS FileServer
Z80+6502/CoPro+Tubes/Econet+SJ - - - - - - - http://www.mdfs.net/User/JGH/