Date   : Tue, 24 Feb 2004 18:32:21 +0100 (GMT)
From   : Johan Heuseveldt <johan@...>
Subject: Re: IDE Interface for BBC

Hi Jonathan,

On Mon 23 Feb, Jonathan Graham Harston wrote:

> I've updated the circuit diagram at
> http://www.mdfs.net/Info/Comp/BBC/Hardware/IDE/8bitcd.gif

That link doesn't work. Went back one level and found '8bitcdv1/gif'.
That's the one you had in mind I suppose?

> which clocks the R/W signal and, yes, it's still doing exactly the same.
>  
> I think I need to just disconnect the phone and not turn up to work for a
> week, so I can sit down and do some proper work on this.

Perhaps reading on what Sprow wrote before, and I wrote on the 5th February,
is a better chance! :-))). Hm, I checked my own story, and indeed I seem to
have a bad day then. Sorry, that English must be difficult to read. And to
many typos as well. :-(((


Let's try again:
In using the cleanup circuits again, all timing is directed to the second
clock phase, creating signals to fast and late. CS in particular

Look at the 8271 (as Sprow suggested), and note that CS is not synchronized
to whatever clock or timing signal, and is dirty as ever can be: all
glitches during address stabilisation are NOT suppressed!
CS's on 8200 devices are a complete other matter than on 65- or 6800 systems,
which can be sensitive for spurious flanks.

As you can see from the 8271, it wil/can receive many, many glitches on its
CS input, which is - pretty much at the start of - in the first clock phase.
In the second phase it is by then stable for quite a long time, giving
the necessary setup times for recognising the RD or WR strobe inputs.

Also, when the 8271 is not selected, it will receive on a constant basis RD
and WR strobes, as it is the R/nW signal directly from the system, although
rebuild/split into RD and WR, which is feed to it.

So whatever is happening, in the 1rst clock phase the CS input may have as
many glitches as the system is generating. Long before the second phase is
entered, the CS signal is stable, wether asserted or not.

The RD and WR are there almost at the start of the 2nd clock phase. But if CS
is not active then, nothing will happen inside the 82xx. This means that a
pretty long time before RD/WR are asserted for a valid access, the CS should
be asserted quite some time before that. Using a cleanup circuit prevents you
to do just exactly that, and comes almost at the same time - or just before
-the RD and WR strobes.

You only need a cleaup circuit, if - and only if - spurious glitches CAN
harm the selected hardware, which is so in many 65-/6800 systems. But now is
not the moment to do so! :-)


So:

 1: Forget the clean up circuit; now it's coming /far/ too late for the RD
     and WR signal as the device haven't processed its selection yet, and
     isn't aware it is selected.

 2: In principle the RD and WR strobe are ok.
 
     But keep in mind that at access, the clock is affected by 'slow down'
/and/ synchronised with the current and fixed 1MHz signal. I'm not sure if
R/nW is following that exactly. I think it is, as the 6502 gets a slow down
clock as an input, and R/nW is synchronised by the that. But in case you have
second thoughts about it, sychronise with two NAND gates, as with the 8271,
but use the 1MHz signal on the 1MHz bus. The following is important too:

Please note the 1MHz signal is a free running clock signal, so could be out
of sync with the normal 2MHz clock. Can this cause trouble at the moment the
IDE device is going to be selected??? I don't know. So in case of any doubt,
synchronise with the 1MHz bus signal, and you can be sure that a
simultanous glitch/occurence of CS with RD/WR in the same clock phase will
never happen, during synchronising the 2MHz clock (stretched 1rst phase) to
the 1MHz clock (fixed timings). The first phase can have different lengths,
and perhaps glitches of addresses /and/ R/nW, which is absolutely forbidden
for these family of devices ,(IDE/8zxx)!
See 'Bray, Dickens and Holmes', page 443.

If not already known, visit:
  <http://www.t13.org/>
  Technical Committee T13 AT Attachment

>From where you can download several documents in PDF about ATA/IDE.
For the Beeb, most likely the ATA-1 and ATA-2 are of interest to you. I
found the ATA-2 more usefull as it had better graphics for timings then
ATA-2 which has only ascii 'graphics'.

Well, I hope I'm more clear now, and more constructive then before.


greetings,
johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
There are more ways into the woods than out.