Date   : Thu, 26 Feb 2004 08:44:51 +0000 (GMT)
From   : Sprow <info@...>
Subject: Re: IDE Interface for BBC

In article <ZoW1+iRPKaPAFwjH@...>,
   Mike Tomlinson <mike@...> wrote:
> In article <Marcel-1.53-0224173221-b49xSBG@...>, Johan
> Heuseveldt <johan@...> writes

> >Please note the 1MHz signal is a free running clock signal, so could be 
> >out of sync with the normal 2MHz clock.

> Are you sure about that?  The various clocks (1Mhz, 2Mhz, 4Mhz etc.) are
> generated from the master 16MHz crystal by the video ULA, so I'd expect
> them to be synchronised.

The 1MHz clock is synchronised to the other clocks as they're all derived
from the same 16M crystal, and it will always have a defined edge
relationship during an access to a slow peripheral (eg.the 6522s), where
necessary the 2MHz CPU clock is slipped to ensure the edge relationship is
constant - and this is some of the logic inside the CPLD in MiniB
 http://www.sprow.co.uk/bbc/minib.htm
Sprow.