Date   : Thu, 26 Feb 2004 12:31:12 +0100 (GMT)
From   : Johan Heuseveldt <johan@...>
Subject: Re: IDE Interface for BBC

Hi Robert,

On Thu 26 Feb, Sprow wrote:
> 
> In article <ZoW1+iRPKaPAFwjH@...>,
>    Mike Tomlinson <mike@...> wrote:
> > In article <Marcel-1.53-0224173221-b49xSBG@...>, Johan
> > Heuseveldt <johan@...> writes
> 
> > >Please note the 1MHz signal is a free running clock signal, so could be 
> > >out of sync with the normal 2MHz clock.
> 
> > Are you sure about that?  The various clocks (1Mhz, 2Mhz, 4Mhz etc.) are
> > generated from the master 16MHz crystal by the video ULA, so I'd expect
> > them to be synchronised.
> 
> The 1MHz clock is synchronised to the other clocks as they're all derived
> from the same 16M crystal, and it will always have a defined edge
> relationship during an access to a slow peripheral (eg.the 6522s), where
> necessary the 2MHz CPU clock is slipped to ensure the edge relationship is
> constant - and this is some of the logic inside the CPLD in MiniB
>  http://www.sprow.co.uk/bbc/minib.htm
> Sprow.

Yes, I know. I ran it two pitfalls:
 1: the problem of the 'open bridge'; depends on the view of what
      traffic stream, although technically there is less doubt perhaps?
 2: with 'free' I meant, compared with the 2MHz clock. The clock itself is
      quite fixed in its timing.
      
    And both are complicated by English not being my native language.

So yes, you're right. The 1MHzE is actually a fixed clock. Both phases of
500 ns never change, because the 100Hz clock needs to be as accurate as
possible. So it is free to 2MHzE; when accessing a 1MHz periphiral, you
don't know where exactly this match the 1MHzE clock. And of course the
1MHzE clock may not be tampered with. It's the 2MHzE which is adjusted to
synchronise with 1MHzE.

Please forgive me for expressing this so vaguely. Sorry faulks.



greetings,
Johan


P.S. to 'sprow':

     May I ask you more about this topic by private email, as this could be
      out of interest to others. In case everyone /is/ interested I'm happy
      to ask here?!
     My guess: it wil be a ripple output, as several FlipFlops get these
      clocks on the Data input as well as the CLK input. So Data must be a
      little late, or CLK a little early.


-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
Never settle with words what you
can accomplish with a flame thrower.