Date : Wed, 14 Apr 2004 17:56:06
From : Johan Heuseveldt <johan@...>
Subject: Re: OVERCLOCKING
Hi Jonathan,
Hi James,
On Wed 14 Apr, Jonathan Graham Harston wrote:
> > Message-ID: <003d01c420bf$837a76e0$35204e51@...>
> "JAMES WATSON" <james@...> wrote:
> > Is it possible to overclock a bbc micro, how would you go about doing
> > this?
Normally I would say that it is not possible.
But I thought I should wait a few days.! :-)
> I recall that the Solidisk 4Meg board did this. I think it had it's own
> faster memory, as well as a fast 6502 CPU.
So there is no real overclocking then, as speeding up is done on another PCB
board and not on the Beep's PCB? Or is it a piggy back system?
> Things you need to bear in mind are:
> * The on-board RAM won't run faster than 2Mhz
Actually it already runs on 4 MHz for the normal 2MHz machine, but no doubt
you know that, trying to ease the explanation. :-)
The 2MHz cycle is divided (*) in 2, to give two accesses to the RAM
per 2MHz cycle. The first is for the video hardware, and the second
is for the processor. Both cycles have their /CAS and /RAS. This is
the hardest part of the design to understand from the BBC drawing.
Any way, both accesses are completely transparent to each other.
*: perhaps not the best explanation, but my route of thinking
is graphicly (/no/ RAS/CAS added!):
2MHz 6502 clock: phase 1 phase 2
_ _________________
|________________| |_
4MHz RAM access: addr'd by 6845 6502 access
_ ________ _______
|________| |________| |_
Screen modes 4, 5, 6 and 7 reads the RAM with 1MHz access, instead of
2 MHZ. So for the 6845 this is likely no problem to use the RAM
memory at 8MHz: it just addresses the same byte four or two times (with
overclocking) instead of two or once as normally, 'thinking' it is
addressing in single accesses.
Indeed I don't think the RAM can be accessed twice as fast, which
wil then be 8 MHz: two 4MHz cycles
> * I/O devices expect to be accessed at 1MHz or 2MHz
> * Sideways ROMs that access I/O devices (eg DFS) often have timing loops
> that depend on the CPU running at 2MHz
The whole clock circuit is tied to other signals generated. I my
opinion it's a hell of a job to disconnect them from each other. In
other words: all the clock signals should be split in clock signals
which should remain at 16,8,4,2,1 Mhz, and which can be twice as much.
As I said, it's AHOAJ.
I have a PCB of a Beeb here (saved from the bin), and I think a
previous owner has tried to do just that: overclocking. The 16MHz
crystal and IC43 are missing. The IC place is fitted with a socket.
Then, all the 40 pins chips are missing: I guess they survived the
experiment and were taken out.
Most likely the RAM has died. I think these RAM chips needs to be
clocked somehow, and wouldn't survive a missing clock? But no doubt
you (Jonathan) can confirm whatever me being right or wrong! :-)
The VIDEO ULA is still there, but I can't try that out in an other Beep,
possibly ruining that RAM as well?
Still haven't done any testing on this Beep; to much other things to do!
Perhaps when there are 48 hours per day/night. :-)
> So, what you would need would be:
> * A faster CPU
> * A faster clock signal to drive the CPU. The system master clock runs
> 16Hz and is divided down to various levels to drive various parts of the
> motherboard. 8MHz and 4MHz are combined to give 6MHz for bits of the
> video. 2MHz and 1MHz go to the CPU, and 1MHz goes to most peripherals.
> * Logic to tell the faster CPU to run an normal speed in situations that
> need it. Probably all I/O access (so pick up the signal that stretches
> the CPU clock), and certain sideways ROMs, (so pick up the ROM select
> value).
>
> So, you'd probably set ROM code speeds to
> DFS: normal, BASIC: fast, VIEW: fast.
The 6MHz is indeed a good example as three clock signals are
meeded: 8, 4 and 2 MHz, which should be unchanged in case of
overclocking. While other circuits - like the RAM - /do/ need
clocks twice as fast. It means a complete redesign, but
implemented on the same PCB. (horror!)
My conlusion: It cannot be done: The work needed is so much, you
cannot sensibly say 'it could be done in principle', IYSWIM :-))
Perhaps another route is the Master, which uses no slow down circuit,
but is based on another technique, which I don't know about.
(see: <http://www.8bs.com/in128.htm> at IC14: 65C12 CPU CMOS 2MHz)
I do hope I'm not too unclear in my writing. I know I'm asking more
than normal from you all in trying to understand my attempts to write
down my thoughts. Please accept my apologies in advance.
I can only hope some improvement is noticable?
But maybe I'm just pessimistic in my hardware views!
But building a HD to the Beep is very, very much easier! I'm sure! :-)))
greetings,
Johan
--
Johan Heuseveldt <johan@... >
aka waarland
The best place is a Riscy place
Beware of the leopard!