Date   : Tue, 25 May 2004 15:05:48 +0200 (BST)
From   : Johan Heuseveldt <johan@...>
Subject: Re: Tube / Master Coprocessor question

Hi Robert,

On Mon 24 May, Sprow wrote:
> 
> In article <40B120C0.6010807@...>,
>    Richard Gellman <splodge@...> wrote:
> > The tube is an asynchronous dual CPU interface. Whats actually happening 
> > is two CPUs running as two independnt systems, with a chip inbetween 
> > (The TUBE, found typically in the second processor box)
> 
> The Tube, as you point out, is the interface specification, not the name of
> the chip.

I think the TUBE ULA is still clear to everyone?
It's the supporting chip for that interface protocol, isn't it? :-)

> > Note that contrary to the expected behavior, the data is not 
> > signalled by interrupts.
> 
> I'd have to disagree there. A cursory disassembly of the IRQ handler shows
> that messaging from the IO processor to the 2nd processor is done
> exclusively with interrupts, and the high speed block data transfers with
> NMIs.
> 
> Maybe you were talking about the host not the parasite?

Yes, I get the feeling he means the host, as he called it the I/O Processor.
Different manuals have different nomenclature. :-)
 

Johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
The hardest thing in the world to understand
is the income tax. - Albert Einstein