Date   : Sat, 11 Dec 2004 16:01:08 +0000
From   : mick@... (Mick Champion)
Subject: Eprog 

Hello everyone, 
 
 
Angus Duggan wrote ; 
 
AD>Mick, you had mentioned putting a 16v 47uF capacitor between pin 7 and 
AD>ground of the TL497A. Did you implement that? 
 
I've just opened up my programmer box and the answer seems to be no. I have 
put an additional 470uf 10v cap to smooth the 5 volt input line. This I found 
necessary as when the TL497A was oscillating (write mode), you could hear 
frequency noise from the BBC's speaker. 
 
 
I also had a problem with the address latching dropping out. The M/Code sends 
the first 8 Lo bits of the ROM address, these are latched by the left hand 
74LS374. The next part of the cycle sends the final 6 bits of the address 
which are latched by the right hand 74LS374. The actual byte to be written / 
read would come next, shortly followed by latch reset, then around again for 
the next address. In my case, the left LS374 would have it's latches reset 
prematurely when the right hand LS374 was being set. In turn, the right 
latches would reset before the write cycle. 
 
 
I presume that an inducted spike caused the unwanted reset at each change in 
the cycle. This not being helped by my veroboard layout / sensitive chips ect.
After playing around, I settled on two 820pf ceramic disc capacitors. One for 
each 74LS374 placed between CK and ground. Please note that although this 
worked for me but I used trial and error, not science. Needless to say too 
high value will stop the latches being reset at the end of full cycle, too low
and your spiked! 
 
 
Angus. You sent me a debug program on the 2nd of May 2002. This allows  
stopping and checking each stage of the 3 part cycle with a meter. I found it 
very useful indeed. If John or anybody else thinks it might help, I will 
forward the mail if you have no objection.   
 
 
   
Mick 
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