Date   : Fri, 12 Aug 2005 09:17:22 +0200
From   : John Kortink <kortink@...>
Subject: Re: 80186 co-pro

On Fri, 12 Aug 2005 07:35:30 +0100, Sprow wrote:

>In article <1123786532.11920.10.camel@...>,
>   Phil Blundell <philb@...> wrote:
>
>[ARM, 6502, Tubes, emulation]
>
>> As far as the Tube ULA goes, my original plan was to use something
like
>> an XC9500 CPLD.  But, having looked at the number of registers
involved,
>> it seems like a CPLD solution would start to get rather expensive; a
>> small FPGA would probably be a better bet.
>
>Yeah, that was my conclusion too. The 24 byte FIFO is a killer: 24*8
FF's
>needed, which for Lattice parts means you need 24*8 logic blocks, such
parts
>are available but costly and usually come in 300+ pin packages.
>
>A small FPGA with distributed RAM is the way, then a can make the FIFO a
 few
>kB long!

And, of course, all this combined with a beeb mobo built
with modern parts, and switchable between B, B+ and Master
mode. Connectors in same place, so it can be put inside
a regular beeb or preferrably Master case. And everything
so far mentioned integrated, i.e. switchable 2p, GoMMC,
improved speech proc.

Two days, tops. ;-)


John Kortink

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