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Date   : Thu, 18 Aug 2005 09:29:15 +0100 (BST)
From   : Greg Cook <debounce@...>
Subject: Re: FDC status register test - please help

On Wed, 17 Aug 2005 19:28:47 +0100, Tom Seddon <tom@...>
wrote:

> Greg Cook wrote:
[...]
> > Some controllers, real and emulated, don't update the track and
> index
> > flags when idle, and it's alleged other boards invert them! (BeebEm
> > declares a board-specific property, TR00_ActiveHigh.)  If that's
> true,
> > how come the drive head doesn't co *crunch* when driven from these
> > boards?
> 
> Presumably because there's a NOT "thingy" somewhere between drive and
> 
> status register, which inverts the relevant bit of the status
> register? 
> As far as I'm aware, that register just reflects what the drive is 
> indicating, so it could be anything, even bits swizzled, without a 
> problem, because the drive never sees any of it.
> 
> Though obviously the software would have to know about that.

Real drives don't go crunch, of course, because even if the software is
confused the 1770 will refuse to step out if track 0 is asserted, and
the input is always active low.  So a board that inverts /TR00 will
show itself to be useless pretty quickly...

Where then?  It would have to mean the 1770 comes in two flavours, or
an inverter on the daughterboard is activated when the status register
is read.  An EOR instruction in the ROM would be cheaper, so now the
rumour seems quite unlikely.

> With opus challenger, I got status register as 0 after each
> operation. 
> The drive control is write only, but I got back &FF in case that's of
> 
> any interest :)

--- "Rob" <robert@...> wrote:
> X1=&0, X2=&FE
> y1=&0, Y2=&FE
> 
> BBC B, Acorn 1770 upgrade, Acorn DFS 2.26.

Of course *slaps forehead*, the controller is interrupted after
official ops.  For anyone interested, here's a revised test that
performs two seeks:

*HELP
?&FE84=&C
PRINT "A=&"; ~?&FE84
?&FE87=&27
?&FE84=&1C
PRINT "B=&"; ~?&FE84

Greg


               
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