Date   : Sun, 05 Mar 2006 03:44:51 -0000
From   : "Mike" <profpep@...>
Subject: Re: Warning: Sad case on list!

> If I want to bust numbers, I'll use the AMD box here, or SSH into a Cray
> or Origin box. (I'm a massive fan of Cray architecture too, now THAT
> would make a nice second processor, though the cooling system would ruin
> the clean lines of the cheese wedge  ;-)
>

< AAmeeting mode >
"I am a BBC sad case and my name is Mike"
</ AAmeeting mode >

American friend reckons he can get a formal logic spec for a Cray1/1A.

12.5nS clock cycle, 64 Bit word,  1Meg + WORDS of RAM.  200,000 gates (all
ECL). Wire quantised in lengths of 1, 2, 3 or 4 feet. Original drew 115KW
from a 230V 3 phase primary, 12 phase polyphase secondary, motor generator
set. Voltages inside the unit, -5.2 and -2.0 volts. Regulation at motor
generator level. Freon cooled. Took 39 square feet of floor space - quite
small. Uses boundary scan test system. Has own minicomputer for IO.

His Kink? He wants a scale model of a Cray 1.

A scale model that actually works

A talk with engineering reps from some of the FPGA stars got them all
thinking. Major problem, as always with 64 bit, is lack of IO pins. Still,
we can get 6nS Static RAM, (running Motorola DSP at 80MHz, needed 7nS to get
0 ws), and probably enough FPGA content to implement the thing. It is a form
of RISC after all. I reckon we could even use the original Cray layout at
1/8 or 1/10 scale. Present thoughts revolve around what to do for host IO?

It would be expensive.

But it would be a very cool toy.

(But for now my personal ambitions lie with one of Sprows ARM Co-Pro's)

By the way if you think we're obsessives, take a look at what the owner of
Armari collects:
http://www.hexus.net/content/item.php?item=903&page=2

||\/||ike




I talked to some peoepl at Altera and Xilinx, after doing the specs for a
real world project