Date   : Sun, 05 Mar 2006 09:27:59 -0000
From   : "David Harper" <dl.harper@...>
Subject: Re: Warning: Sad case on list!

"Fragula" <fragula@...> wrote (amongst other things):

> <NMI>
> Which Reminds me, who remembers the general formula for clock cycles vs
> DRAM access cycles, more specifically for the 80186?
>
> Standard issue are 150nS, which is summit like 6.6MHz if you allow for a
> fetch for every clock cycle. Yet the 80186 runs at 10MHz. Now I know
> this is wrong, but i can't remember why.

I am intending to put together a few web pages principally about the Master
512 (which I did quite a lot of work on at one stage). For the time being I
have just stuck up one or two items, including the data sheet for the 80186.
You can find it here:

http://uk.geocities.com/curried.onion@btopenworld.com/bbc-computer/master512/info.html

(This sheet was produced by AMD, but their version of the 80186 was totally
interchangeable with Intel's. This was before their disagreement over the
licensing of the name 80386, and Intel being told it could not claim a
number as a trademark.)

Please note that my site will not remain at this URL - it is an awkward
address with very limited facilities. This is simply temporary until I get
something sensible organised, so please do not link anything else to it.

David Harper