Date   : Thu, 03 Aug 2006 17:13:38 +1000
From   : "Richard Wilson" <rich@...>
Subject: Video ULA

Hi All,

This is my first post here, so hello to everyone. I haven't used a BBC
for
nearly 20 years, but I used to love the machines and did a lot of
experimenting and a little programming on them back in the day. These
days
I'm pretty involved in the Amstrad CPC community and develop a CPC
emulator
called WinAPE (http://www.winape.net).

I'm also developing a multi-platform emulator called JEMU (don't bother
with
the URL yet since the version there is really old, but if you really
must
http://jemu.emuunlim.com, and it don't work well with Firefox). Recently
I've decided I should do some more development for it, and implemented
much
improved versions of the CPC and VZ emulators, and made some attempt at
emulating the ZX80/81. These are all Z80 machines, so it wasn't too
difficult to get them all up and running. I was after an excuse to do a
6502
machine, even though I hadn't used a 6502 for 20 years, so I decided to
put
BBC Model B emulation into JEMU. Things are going pretty well, except
for
some keyboard problems I'm having... Even got Revs working now, and not
sure
about Exile due to the keyboard problems.

In the process of developing the JEMU BBC core, I've been doing a lot of
research, and looking into the BBC schematic etc for insight (and some
messages on this board), and found a few things which I'd like to share
with
everyone here... especially other emulator developers.

1. I discovered exactly how the Video ULA works, and how it maps the
palette
for the various modes. All 8 hardware modes are really quite simple. Bit
4
is simply (and only) the CRTC clock rate. It doesn't affect the
resolution
or palette. Bits 3 and 2 are a simple delay count for an internal shift
register, providing 8 cycles (00), 4 cycles (01), 2 cycles (10) and 1
cycle
(11) respectively (these are 16MHz cycles). The shift register fills the
new
bits with 1's. The CRTC clock rate determines when new data is fed into
the
shift register, and that's either 8 cycles (when clocked to 2MHz) or 16
cycles (when clocked to 1MHz). Every pixel always uses bits 7,5,3 and 1
to
determine the palette index, combined with the current Flash bit.

2. I discovered something I didn't know after years of working with the
6845. It actually inserts a "dummy" scan row in every even field when in
interlace mode. Without this, it's impossible to get Revs synchronized
the
way it should be. I had previously assumed the interlace VSYNC was
delayed
every second frame, and operated normally on the odd fields... Maybe a
different CRTC type does (what type of 6845 is in the Model B standard?
HD6845?).

Hopefully I'm only a few weeks away from having something new to put on
the
JEMU site..

Cheers,
Richard