Date   : Fri, 13 Oct 2006 11:49:30 +0100
From   : "David Harper" <dl.harper@...>
Subject: Re: Tube Documentation

Jonathan Graham Harston wrote:

> Indeed. When I was coding some coprocessor code back in 1990
> (eek! sixteen years ago!) A particular gotcha is that 256-byte
> write has a terminating ack, whereas 256-byte read does not.

It is not an ack byte. The reason for it is that the DRQ line from the Tube
ULA is active on the parasite side whenever the Host-to-Parasite Register 3
contains data or the Parasite-to-Host Register 3 is empty (the two registers
are quite separate, despite the names). This means that for normal use,
H-to-P Reg 3 must be kept empty, but P-to-H Reg 3 must be occupied.
Interrupt-controlled protocols (i.e. 0 to 3) will do this automatically, but
the 256-byte transfers are not interrupt driven. This means that on a type 6
transfer an extra byte must be written after the 256 bytes of data to make
sure that P-to-H Reg 3 is occupied. If this were not done then DRQ in the
parasite would remain active, and this is normally conencted to the NMI
input of the parasite processor. (The 80186 does things differently, as we
have come to expect!)

This is also the reason for the two BIT instructions in the Tube host code
for data transfer types 0, 2 and 6. These are not testing anything. They are
simply pulling off the bytes left from last time which keep the register
occupied. (There might be one byte, or there might be two. If there is only
one then the second BIT instruction does nothing, since they occur before
any data has been put into the register by the client.) BIT is used simply
because it reads data off the Tube register without affecting A, X or Y in
the 6502.

David Harper