Date   : Thu, 23 Aug 2007 13:49:43 +0100
From   : julesrichardsonuk@... (Jules Richardson)
Subject: M512 copro schematics?

Phil Blundell wrote:
> Let me know when you finish tracing the '286 board.  I keep meaning to
> try to debug what's wrong with the ones I have.

It's a substantially different animal to the 80186 board it seems...

Clock generation and reset control is handled by a D82284 IC.

The CPU address bus is isolated from the rest of the system by three latches. 
A0 isn't used by the ROMs, TUBE or floating-point unit at all; A1..xx from the 
CPU latches map to A0..xx for the ROMs, TUBE etc. - presumably something to do 
with the way the '286 fetches words from memory.

Memory control is handled by three PAL chips. There are four banks of RAM, all 
with 9 commoned address lines (a valid address is latched into the RAMs in two 
stages). Data lines (Din + Dout) are commoned between banks 1,3 and 2,4. /WE 
and /RAS are commoned between banks 1,2 and 3,4. The lower 8 memory address 
lines run via a set of resistors, but the upper 9th line doesn't (I've not 
figured out why that one's special yet).

For bonus points, there's an 8-bit latch on the lower 8 CPU data lines which 
doesn't actually do anything: the outputs are shorted to the inputs (via PCB 
traces; not a post-production mod). I'm guessing they worked out that they 
didn't need to decouple those lines after all and changed the PCB artwork - 
but I'm not sure why they carried on fitting the chip if so!

There's a few mod wires and cut traces on my board (an issue D) but not too many.

Far as I know the '286 board pre-dates the Master 512 (as the '286 boards 
proved too expensive to rework for that machine), which probably explains the 
complexity - I guess they managed to sort out all the niggles by the time the 
80186 board came along. (Also explains why these boards would run with only 
256K of memory when the M512 had twice that)

cheers

Jules