Date   : Wed, 27 Feb 2008 10:54:42 +1100
From   : msmcdoug@... (Mark McDougall)
Subject: BBC FPGA Boots to BASIC... almost...

Jonathan Graham Harston wrote:

> If the 6502 core implementation is not clears 'B' on a hardware
> IRQ, then when an IRQ happens after a BRK, then the 'B' is still
> set and the MOS will try to deal with it as a BRK. That would
> cause problems as the error handler would be repeatedly
> re-entered, pointing to arbitary machine code rather than an error
> block.

It would appear that this is indeed the case!!! :O

I started to look at the behaviour within the ISR, and noticed that *every* 
interrupt after a BRK instruction was vectoring to the BRK handler.

Looking at the guts of the 6502 core - in particular the P register - on the 
logic analyzer shows that once the "B" flag is set, it is never reset! Hence 
the endless looping into the BRK handler and eventual freeze.

And yes, I'm (now) aware of the B "flag" particulars. The 6502 core *does* 
actually implement the B bit within the P register. Obviously this, and the 
fact that it is never reset, is a problem...

I've contacted the author and await his response. I'm not familiar enough 
with the workings of his 6502 core to attempt a fix myself, without 
investing some time in studying the code. So I'll see if he agrees that it's 
a bug and has the time to fix it...

Phew - this has been a time-waster! I must admit I was loathe to blame the 
core when there were so many things I could've been doing wrong...

Thanks again to all, especially JGH!
Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"