Date   : Thu, 06 Mar 2008 02:03:21 +1100
From   : msmcdoug@... (Mark McDougall)
Subject: FPGA BBC - yah!

nicola giacobbe wrote:

> I, for one, will pick it up and try to extend in my free time, I love the
> idea and lack the time, a common combination as it seems.

Heh, ain't that the truth! ;)

> Many thanks to you. While I cannot obviously speak for the other listers
> I've enjoyed a lot this ride into Beeb's 'interiors'. 

One thing I forgot to mention - the cpu clock speed is currently hard-wired 
to 1MHz. One thing I did (do) intend to change is to up the speed to 2MHz, 
which should be trivial given the current design (I had it running at 2MHz 
early on). In fact, there's no technical reason to throttle the speed down 
to 1MHz when accessing the "slow" bus, for example, though that could also 
be done (with more effort) to match the real BBC speed... the whole system 
is in reality clocked at 32MHz atm!

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"