Date   : Sat, 08 Mar 2008 00:56:43 +0000
From   : jgh@... (Jonathan Graham Harston)
Subject: TUBE chip, accessing 'Parasite' side

Johan Heuseveldt wrote:
> This is not what I meant. It is the actual /single/ access-cycle the
> coprocessor is doing to the TUBE chip, not the number of cycles (plural) the
> software takes to process things.
 
The only thing AppNote4  says about this is the timing diagram on
page 11 which requires the Tube ULA to respond to parasite NRDS
and NWRS at 110ns min, to meet 4MHz access requirements. I can't
remember how fast Acorn's ARM CoPro runs at. Sprow's runs at
64MHz, the Tube ULA is incorporated within the FPGA, so is
physically a differnet component.
 
> (I do use BS to switch RAM for vector access)
 
I only have a 6809 programming sheet, I don't know what the
hardware signals do (other than the ususal ones - NMI, R/W, etc.)
What does BS, BA, Q, BREQ do?
 
-- 
J.G.Harston - jgh@...                - mdfs.net/User/JGH
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