Date   : Sat, 08 Mar 2008 07:47:13 +0000 (GMT)
From   : info@... (Sprow)
Subject: TUBE chip, accessing 'Parasite' side

In article <080308015507@...>,
   Jonathan Graham Harston <jgh@...> wrote:
> > Message-ID: <Marcel-1.53-0304133311-b49xSBG@...>
>  
> Johan Heuseveldt wrote:
> > This is not what I meant. It is the actual /single/ access-cycle the
> > coprocessor is doing to the TUBE chip.
>  
> The only thing AppNote4  says about this is the timing diagram on
> page 11 which requires the Tube ULA to respond to parasite NRDS
> and NWRS at 110ns min, to meet 4MHz access requirements. 

My reading of it was also that it's a 4MHz rated part, but that of course
the host side is only ever accessed at 2MHz.

> I can't
> remember how fast Acorn's ARM CoPro runs at. Sprow's runs at
> 64MHz, the Tube ULA is incorporated within the FPGA, so is
> physically a differnet component.

The FPGA is also clocked at 64MHz, but that's clocking a state machine so
the parasite side can't actually be accessed that fast. The processor's IO
window is configured as 1-4-3 cycle access, so 8MHz, the host side is
govered by the phy2 clock so is 2MHz as ever,
Sprow.