Date : Sat, 08 Mar 2008 15:46:55 +0100 (GMT)
From : johan@... (Johan Heuseveldt)
Subject: TUBE chip, accessing 'Parasite' side
Hi,
On Sat 08 Mar, Jonathan Graham Harston wrote:
> > Message-ID: <Marcel-1.53-0304133311-b49xSBG@...>
> Johan Heuseveldt wrote:
> > This is not what I meant. It is the actual /single/ access-cycle the
> > coprocessor is doing to the TUBE chip, not the number of cycles (plural) the
> > software takes to process things.
>
> The only thing AppNote4 says about this is the timing diagram on
> page 11 which requires the Tube ULA to respond to parasite NRDS
> and NWRS at 110ns min, to meet 4MHz access requirements.
Thanks for pointing that out. I'll read it more closely, as this indeed is
important to check for the maximum speed during an access cycle.
> I can't remember how fast Acorn's ARM CoPro runs at. Sprow's runs at 64MHz,
> the Tube ULA is incorporated within the FPGA, so is physically a differnet
> component.
Quite! :-)
> > (I do use BS to switch RAM for vector access)
>
> I only have a 6809 programming sheet, I don't know what the
> hardware signals do (other than the ususal ones - NMI, R/W, etc.)
> What does BS, BA, Q, BREQ do?
6502 SYNC is signaling an opcode fetch. This is used to link code in an
certain area to the data area: Bank switching in hardware. The Master uses
this extensively around the Normal/Shadow RAM in conjuction with the VDU
code at &8000 - &9FFF.
There's no similar SYNC concept on the 6809, but two output signals show the
current state of the processor, and can be used to put the vectors elsewhere
instead of putting the normal code elswhere. One of these schemes is needed
c.q. wanted by me, as the end of TUBE OS JMP table overlaps the hardware
vectors. As an exercise I wanted the call addresses to be the same as in the
6502 2ndP. I also provided a way to access and rewrite the vectors!
BTW, these addresses are also the same in the Z80 2ndP.
DMA/BREQ is an input, requesting ownership of the 6809 busses. DMA being
an example. When granted by the 6809, the 6809 puts all busses, and some
control lines, into hi-Z.
BA = bus available
BS = bus status
BA BS description
0 0 normal (running)
0 1 Interrupt or Reset aknowledge
1 0 SYNC aknowledge
1 1 Halt/Bus Grant aknowledge
So BA/BS=01 can be seen as a Vector Pull. I'll use that to switch to the
appropiate RAM locations, only needing A8 to toggle; FFFx > FEFx, as these
16 bytes are not used because I/O is mapped there, including the TUBE.
Greetings,
Johan
--
Johan Heuseveldt <johan@... >
aka waarland
The best place is a Riscy place
Ten years of rejection slips is nature's way of
telling you to stop writing. - R. Geis