Date : Sat, 08 Mar 2008 16:42:22 +0100 (GMT)
From : johan@... (Johan Heuseveldt)
Subject: TUBE chip, accessing 'Parasite' side
Hi Robert,
On Sat 08 Mar, Sprow wrote:
> In article <080308015507@...>,
> Jonathan Graham Harston <jgh@...> wrote:
> > > Message-ID: <Marcel-1.53-0304133311-b49xSBG@...>
> > Johan Heuseveldt wrote:
[the single access cycle to the TUBE chip / Sprow'w ARM CoPro]
> > The only thing AppNote4 says about this is the timing diagram on
> > page 11 which requires the Tube ULA to respond to parasite NRDS
> > and NWRS at 110ns min, to meet 4MHz access requirements.
>
> My reading of it was also that it's a 4MHz rated part, but that of course
> the host side is only ever accessed at 2MHz.
I think I need to print this out, as reading from screen is not realy
comfortable, and need for rereading is a bit clumsy.
Although page 2 states (quoting)
'The processors are synchronised with one another ...',
it still doesn't secure me enough wether or not some slow-down or clock
stretching triggered by contention logic is desirable.
> The FPGA is also clocked at 64MHz, but that's clocking a state machine so
> the parasite side can't actually be accessed that fast. The processor's IO
> window is configured as 1-4-3 cycle access, so 8MHz, the host side is
> govered by the phy2 clock so is 2MHz as ever,
> Sprow.
In some designs two 6522 are backed to each other, indeed giving full
asynchronous access on each side of the processor side of them. Not too
difficult to imagine something similar on register level in the TUBE chip,
although a bit more advanced than just two 6522's.
No doubt you also have to deal with that in the FPGA design?
The problem is that I would find the quoted line - see above - from
document '004' clear enough, until I saw the slow-down/stretching and
contention circuits of the 6502 2ndP.
I wonder, Robert, could you enlighten me please?
Would be very gratefull to you,
Johan
--
Johan Heuseveldt <johan@... >
aka waarland
The best place is a Riscy place
It's easy to be brave from a safe distance.