Date   : Sun, 09 Mar 2008 22:58:55 +0000 (GMT)
From   : info@... (Sprow)
Subject: TUBE chip, accessing 'Parasite' side

In article <080309015504@...>,
   Jonathan Graham Harston <jgh@...> wrote:

[contention logic] 

> Now that I think I know what you're talking about, though, I see
> that the 6502 and Z80 copros feed PCS and HCS into an OR that
> feeds the timing circuitry - probably your cycle stretching.
> Interestingly, the 32016 and 80186 copros don't.
 
More likely I would suggest that there's a possibility for a race condition
if one processor is writing to one side just as the other processor is
reading (polling) the same register other side. 

Presumably the Z80 and 6502 sample the bus as a point where it would be
possible to see the asynchronous transition of the bit from the other side
and end up with a misread value (eg. some status bits changed others not due
to varying propagation delays through the logic paths in the Tube chip).

Tha 80186 ans 32016 maybe latch at a different point in the cycle so the
race condition went away.

In my ARM coprocessor as I had a higher rate clock available (ie. something
other than the host's phy2) it was easier to just double buffer the results
so I could guarantee that polled reads from one side would only change bits
during the idle states,
Sprow.