Date   : Sat, 22 Mar 2008 19:52:00 +0000
From   : jgh@... (Jonathan Graham Harston)
Subject: New 6809 TUBE

I've been away for a few days, so I'm entering this thread a bit
late...
 
Johan Heuseveldt wrote:
> Sometimes the several design options don't allow for two
> seperate bank switch registers, as I'm running out of GAL in-
> and outputs. In fact I also need three other bits for the
 
Eurghhh!!! I *hate* designes that use PALs and GALs. You just have
an annonymouse black box in the middle of the design with no idea
what it does and no possibility of reproducing it. Is your design
really so complicated that you can't implement it with a couple of
logic ICs? If it is that complex, it's too complex.
 
A quick bit of scribbling (not knowing exactly what you're trying
to implement, and what your bank sizes are) suggests a 8-in NAND
and two halves of a 2-to-4 decoder for I/O selection, an XOR for
vector selection, and the rest of the XOR gates for a couple of
inverters.
 
For banked memory, you could have a quick look at
http://mdfs.net/Info/Comp/Z80/Circuits/1MbMem.gif
 
If you clarify a bit what memory banking system you're aiming
for and what hardware I/O you're looking at (obviously, Tube)
I can scribble something together.
 
Something that may influence the design is if you use BA/BS to
toggle A9 instead of A8, so putting the hardware vectors at
&FDFx instead of &FEFx, then it makes decoding for hardware
easier if there's more than just the Tube ULA. It means all
of &FExx-&FEFF is I/O, instead of &FExx-&FEEF.
 
-- 
J.G.Harston - jgh@...                - mdfs.net/User/JGH
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