Date   : Mon, 24 Mar 2008 23:30:44 +0100 (GMT)
From   : johan@... (Johan Heuseveldt)
Subject: New 6809 TUBE

Hi Jonathan,

On Mon 24 Mar, Jonathan Graham Harston wrote:
> > Message-ID: <080322205505@...>
> jgh@... (Jonathan Graham Harston) (Jonathan Graham Harston)
> wrote:

> > If you clarify a bit what memory banking system you're aiming
> > for and what hardware I/O you're looking at (obviously, Tube)
> > I can scribble something together.

It is my design. Why should you worry about that. :-))

[snip]

> Adding MMU, based on 1MbMem.gif above, you could use a '157 4 time
> 2-to-1 selector, '89 16*8bit RAM and '245 8bit buffer.

That's how I designed the FLEX version, although I've used 219s, which is
more sensible with the big RAM chips available these days. Later I discovered
the SWTPC boards that indeed use the 189 for that. 
>  
> I've put a few notes at http://mdfs.net/Info/Comp/6809
>  
> > Something that may influence the design is if you use BA/BS to
> > toggle A9 instead of A8, so putting the hardware vectors at
> > &FDFx instead of &FEFx, then it makes decoding for hardware
>  
> Or toggle A7 to put vectors at &FF7x.

The hardware is assigned to &FEF0 to &FEFF. The RAM there is thus unused, so
I made that available to the 16 locations for the HW vectors. That the
most logical thing to do, and most simple as well. Why making an extra
gap in the software space?

These locations for the vectors can still be accessed by putting a vector
number 0-7 into location &FEFD and the two vector locations are available at
&FEFE and &FEFF. The real discrete logic is no fun at all, but the boolean
expressions for the GAL is rather simple. So &FEFD is the Vector Select
Register. Other locations are for bank select registers, and something secret
about interrupts! :-))
(I'll explain later when the schematics are published)


Johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
Don't look now, but there is a
multi-legged creature on your shoulder