Date   : Mon, 02 Mar 2009 15:32:00 +0000 (GMT)
From   : tommowalker@... (Tom Walker)
Subject: Fwd: New Screen Modes with ARM7 Co-Processor?

> >Why does it need to be linearly addressable?
> 
> Because the CRTC needs it to be. Why is that so hard to understand ?

I think (hope!) that you will find the following two pieces of evidence convincing.

The first is the program at the bottom of this mail. Run it on a Master 128
in modes 0,1 or 2 and watch as a magical non-existant 40k 512-line mode appears!

The second is the disc image at
http://b-em.bbcmicro.com/interlace.ssd
which actually displays a picture using the code. Only 512x342, but that's
because of the choice of picture (a Mac 128 screenshot) rather than any technical
problems (replace the files C1 and C2 to show this).

Tom

   10 DIM CODE% 400
   20 FOR PASS=0 TO 3 STEP 3
   30 P%=CODE%
   40 [OPT PASS
   50 SEI
   60 LDA #8
   70 STA &FE00
   80 LDA #3
   90 STA &FE01
  100 LDA#4:STA&FE00:LDA#77:STA&FE01
  110 LDA#7:STA&FE00:LDA#68:STA&FE01
  120 LDA#3:STA&FE00:LDA#&48:STA&FE01
  130 LDA#9:STA&FE00:LDA#6:STA&FE01
  140 LDA#5
  150 STA&FE00
  160 LDA#1
  170 STA&FE01
  180 LDA#6:STA&FE00:LDA#63:STA&FE01
  190 LDA#(IRQRT MOD256)
  200 STA &204
  210 LDA#(IRQRT DIV256)
  220 STA &205
  230 LDA #&7F
  240 STA&FE4E:STA&FE6E
  250 LDA#&C2:STA&FE4E
  260 CLI
  270 .HALT JMP HALT
  280 .IRQRT
  290 TXA:PHA:TYA:PHA
  300 LDA&FE4D:AND#2:BNE VSYNC
  310 LDA#&40:STA&FE4D
  315 NOP
  320 LDA#1:STA&FE34
  330 PLA:TAY:PLA:TAX:LDA&FC:RTI
  340 .VSYNC STA&FE4D
  350 LDA#0:STA&FE34
  360 LDA#&FB:STA&FE44:LDA#&28:STA&FE45
  370 PLA:TAY:PLA:TAX:LDA&FC:RTI
  380 ]
  390 NEXT