Date   : Thu, 19 Mar 2009 17:10:55 +0000
From   : splodge@... (Richard Gellman)
Subject: Hardware questions

On Thu, 19 Mar 2009 16:08:55 -0000, "Mike" <profpep@...> wrote:
> According to the Master 128 Reference Manual Volume 1:
> 
> &FCFF is the paging register.
> 
> "Page &FD, (with the exception of &FDFE and &FDFF) is reerved for code.
> This
> allows, for example, cartridges to put part of their program(s) into the
> memory map without paging.
> 
> &FDFE and &FDFF are the Test software indirection locations."

Ah... now this is different again. So the top two bytes are indirections.
Would I be correct in saying that as long as no test software is loaded,
these can be used for data? I'm assuming the MOS itself doesn't use these
otherwise it would be jumping to random data.
 
> (Master 128 Reference manual Pages F6.6 - F6.7)
> "Since the paging register is a write-only latch, location &00EE in the
> zero
> page of the BBC machine addressmap has been allocated as a RAM image of
the
> register. Note that this location will remain in the I/O processor's
memory
> map if a second processor is fitted.
> 
> The importance of this image is that it allows interrupt routines to
change
> the paging register and restore itagain afterwards.
>
> It is vital to change location &00EE BEFORE changing the paging register
> itself. It you do not, then an interrupt may occur before you change the
> RAM
> image and this will restore the paging register to the old value of &EE."

Seeing as I plan to use my own paging register, I assume I can disregard
that &EE changing and just use a plain register for specifying the top 8
bits of an address?
 
> On older doco, Acorn reserved the lower 32K of  extended memory for their
> own use, still allowing 32K of user space. I think I once ran a unit with
a
> Dallas Smartsocket with a 62256 CMOS RAM in it accessed in this way. It
> gave
> me 32K of battery backed data logger space, for ON a 'B' you could use a
> 'SmartWatch' and use the clock, though the access code was a bit weird,

The device I'm planning to build will require a 32K-and-a-bit (the bit
being a matter of bytes) address space. I don't have any 1Mhz bus devices
that use paged memory (to my knowledge, unless the Music 500 synth does),
so if I read all of this right, I should be safe in using the lower 32K
address space as well, with a 256-byte window at FD00-FDFF.




Anyone got any offers on a Plus 3 circuit diagram? :)

-- Richard