Date   : Thu, 16 Apr 2009 11:50:45 +0100
From   : philb@... (Phil Blundell)
Subject: ReCo6502 now available

On Wed, 2009-04-15 at 20:09 +0100, Michael Firth wrote:
> A secondary problem then probably becomes level translation, as the Xilinx 
> part only has up to 3.3V I/Os. There are 5V capable Xilinx parts, but they 
> are very old, and hence now very expensive.

The ULA (equivalent) doesn't need to actually output 5VCMOS levels, does
it?  Assuming that 3.3V drive is adequate, which I guess it probably is
for the Beeb, you could use a simple buffer (QS3245 or something) to
reduce the incoming 5V signals to a level that your FPGA/CPLD can
tolerate.  (Of course, 3.3V I/O is itself starting to disappear on newer
FPGAs, and this trick probably wouldn't work for any lower signalling
voltages.)

I did start work on a ULA workalike using some kind of Spartan-3 FPGA a
year or so back, but I managed to get one of the IC footprints
hopelessly wrong on the PCB (I think I put down a TQFP device but used
the pin ordering for PLCC, or vice versa) which made it impossible to
assemble the things and I never found time to re-spin the layout.  In
the meantime I have a feeling that one of the other parts I was using
has gone obsolete so it'd probably take a fair amount of warming over to
resurrect that design.  Still, it might still be an interesting thing to
try again one day.

p.