Date   : Sat, 06 Jun 2009 12:44:45 +0000 (GMT)
From   : tommowalker@... (Tom Walker)
Subject: 65C02 instructions

> 1. Zero Page Relative addressing
> Is it correct to assume the second byte of the instruction is the page 
> zero location, and the third byte is the branch offset? I guess this 
> because it'll want to check PZ before worrying about the branch.

Yes. These instructions aren't in the 65C102 chips used in Acorn kit though.

> 2. Would the code for the TRB instruction look like this:
> ? ? ???CPU.A = (CPU.A Xor &HFF) And CPU.Temp
> ? ? ???Memory_Write CPU.A,CPU.Addr
> ? ? ???CPU.PS.Z = ((CPU.A And CPU.Addr) = 0)

No. TRB and TSB don't change the accumulator. B-em's implementation of TRB
looks like

temp=readmem(addr);
p.z=!(temp&a);
temp&=~a;
writemem(addr,temp);

and TSB is 

temp=readmem(addr);
p.z=!(temp&a);
temp|=a;
writemem(addr,temp);

Tom