Date   : Sat, 20 Mar 2010 17:28:36 -0700 (PDT)
From   : flynnjs@... (Jason Flynn G7OCD)
Subject: BBC FPGA Boots to BASIC... almost...

Hi Anders,
   where did the project end up? Is there's anything available to
tinker with?

more below,
  Jason

--- On Sat, 20/3/10, Anders Carlsson <anders.carlsson@...> wrote:
> It appears the message Mike replied to was posted on Feb
> 27, 2008. That > is a little more than two years ago, but
> good discussions never die. :-)

Very true. Looks like I can chip in... further along in the thread...

Mark McDougall wrote:
> Michael Foot wrote:
> > They need to return &FE instead. ie. the high part of the address.
>
> Ummm, OK, but can you explain why that's the case?

I can. As the CPU reads something like LDA &FE60 from memory, prior
to execution, the data bus transfers &AD, &60, &FE.
The address bus is then set up &FE60 and the read occurs. If no
data is driven onto the bus (say due to non-decoded address) then
the CPU will see the previous bus data held there capacitively.

This is easily proven by setting up ROMSEL to an empty socket and
reading the contents. You'll get 256x &80 then 256x &81 etc...

I found some weak contention on the bus recently when my empty ROM
sockets were reading back &FF. (Empty socket not to be confused with
blank ROMs in a socket which really do return &FF !!)