Date   : Tue, 06 Apr 2010 17:40:00 +0100
From   : philb@... (Phil Blundell)
Subject: "open" beeb bits...

On Tue, 2010-04-06 at 17:22 +0100, Philip Pemberton wrote:
> Jules Richardson wrote:
>  > The TUBE ULA's obviously one - same with the video ULA.
> 
> The TUBE ULA could probably be reimplemented in a CPLD if you were that 
> way inclined. You could most likely stuff a coprocessor core (say, a 
> Microblaze or a Picoblaze) and the ULA bits into a modern entry-level FPGA.

Yeah, we had quite a long discussion about that a year or so back.  The
number of registers that you would need to implement the full-size VDU
FIFO might be a bit of a struggle in a CPLD, but it would be easily
doable in an FPGA.  Or, as John appears to have done, you can just make
the FIFO smaller; I doubt there is much code which relies on being able
to stuff a full-length VDU sequence in there without blocking.

I did start work at one point on an FPGA implementation of a 6502 core
plus Tube ULA.  If I remember right it fitted fairly easily into a
smallish Spartan-3.  Unfortunately I botched the PCB layout badly enough
that I couldn't actually assemble the things, and I never found the time
to respin it.

p.