Date   : Wed, 27 Oct 2010 22:39:05 +0100
From   : mfirth@... (Michael Firth)
Subject: Reversing the Tube ULA (destructively)

  On 27/10/2010 21:55, J.G.Harston wrote:
> Michael Firth wrote:
>> needed for some specific re-implementations (e.g. the DMA functions used
>> on the 80186 Co-Pro)
> The 80186 doesn't use the DMA functions. The NMI from the Tube is
> connected to the *80186's* DMA input pin instead of the 80186's NMI
> pin. Transfers are still done as Tube NMI interupts, it's just that
> the 80186 sees the Tube NMI interupt as a DMA interupt.
>
>> implementation. This category is hard to be definitive about, but I
>> think it includes the ULA "soft reset" and the "parasite reset" bits in
> I've used the Reset function, and some SJ network utility tools also
> use it.
>
I think my list was trying to serve two functions with one list - 
listing things that could potentially be left out of a re-implimentation 
(e.g. Host IRQ), and things that would need specific testing in a new 
implementation as they aren't used by default (e.g. the two reset bits)

Not implementing the two reset bits would be a somewhat small saving, 
unless you were implementing in a very small programmable logic device. 
As they don't need any external connectivity, then leaving them out 
doesn't save any pins, which can potentially be useful.
>> implementations. I think the "Host IRQ" feature and control logic is in
>> this class, as the pin is not (by default) connected to the host on all
> For years I've toyed with writing something that uses the Host IRQ signal
> to do some sort of parallel processing, but have never got around to
> doing it.
>
I think that an application that requires someone to write their own 
Tube handling code, and to have modified hardware available is a pretty 
corner case, for which an original ULA could be used.

One big advantage of leaving Host IRQ off is it makes the (used part of 
the) host side of the Tube interface fit within 16 bits, and, 
potentially even better, you have 8 bi-directional and 8 uni-directional 
signals.

I think that not connecting or level translating the extra 3 address 
lines on the Tube connector is fairly safe, but for a full FPGA 
implementation may be tempting.

Regards

Michael