Date   : Wed, 14 Dec 2011 19:18:31 +0100
From   : kortink@... (John Kortink)
Subject: 32016 + 32082

On Wed, 14 Dec 2011 18:20:02 +0100, Eelco Huininga <eelco@...>
wrote:

>[...]
>
>Interesting find, this 2nd processor.  If you take a look at the Pandora 
>v0.61 code you will find that it reads the configuration jumpers, and 
>depending on wether or not bit0 and bit1 are set, it will set the FPU 
>and MMU flag in the configuration register of the 32016 CPU:

That's interesting.

>[...]
>
>Also, if you look at the photo of your 32016 board you'll see that there 
>are two jumpers set on the configuration jumper block, which would mean 
>that both the FPU and MMU are present in the config jumpers. But... the 
>buffer chip, which presumably should be fitted as IC16, isn't mounted, 
>so the jumpers can never be read by the software!

That's not true. The G and H jumpers, which are actually
fitted, are not tracked to IC16, but to IC19, pins 5 and
12 respectively.

>Now, if you look at the Pandora v2.00 code, the setcfg[] instruction is 
>used just once, to set the FPU flag (the setcfg[] instruction is used to 
>set the CFG-register of the 32016). The configuration jumper register is 
>never read.

It probably is.

The 32016 also reads, reset time, (and this is most likely
connected to LK4) whether or not address translation (e.g.
by the MMU) is available or not (and the SETCFG instruction
should subsequently enable MMU instructions).

>This might suggest that they explored the use of a MMU during the 
>development of Pandora v0.61 but abandonded it by the time Pandora v2.00 
>was developed, or that they moved MMU functionality from the firmware to 
>software.

The latter is more likely. Pandora is basically just interface.
The OS can decide by itself to enable or disable the MMU under
particular circumstances, regardless of what Pandora does or
doesn't do.


John Kortink

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