Date   : Tue, 26 Feb 2013 19:31:04 +0000
From   : percy.p.person@... (Ed Spittles)
Subject: Qudos MINICHIP / Quickchip ECAD and Ferranti ULA

Hi Phil

On 26 February 2013 00:06, Philip Pemberton <philpem@...> wrote:

> In my long-running tradition of obscure requests...
> [snip]
>
> I'm also interested in a copy of any documentation on Ferranti ULAs -
> databooks, details on the logic cells (specifically the ULA9C series but
> ULA5C may also be useful), design software (or documentation thereof)
> and so on. Examples:
>
>   Qudos Ltd. - Qudos Logic Array Design Software Manual QED2 (pub. 1986)
>
>   Ferranti - Ferranti ULA Design Manual A/F002 (pub. 1981)
>

I have some imformation in my mail archive:

Here are a couple of links:

- a page of a document describing the (related) R series, which
confirms that all designs are NOR based - this probably tells us that
storage is done by cross-coupled NORs.
http://www.cl.cam.ac.uk/~atm26/acorn/electron/ula/ferranti-r-series-cell.png

- clean copy of a ULA cell
http://www.cl.cam.ac.uk/~atm26/acorn/electron/ula/asic_1a.png

See also this post about the Electron ULA which has been photographed
(is in a lidded package)
http://lists.cloud9.co.uk/pipermail/bbc-micro/2010-November/009620.html

and this earlier thread about the Tube ULA (which is expoxy encapsulated)
http://lists.cloud9.co.uk/pipermail/bbc-micro/2010-October/009365.html

These ULAs are bipolar devices, a regular array of cells each of which has
current sources, resistors and pulldown transistors.  The customisation is
just the single metal layer: all the via cuts are already in place.  It
looks like the metal is laid out on a grid, so there's very little
information needed to get the circuit.  Each cell is probably configured as
one or a few logic gates.

Here's a (rough) composite of the ULA cell - I patched together uncovered
sections of several cells:
http://img600.imageshack.us/img600/6418/ulabackground1cell.png

And here's an explanation of the previous-generation ULA cell:
http://img831.imageshack.us/img831/9233/ulacell.png

I've rotated the photo of the ULA cell, and labelled some pins:
http://img337.imageshack.us/img337/2070/ulacellcompare.png

There are four logic inputs and two logic outputs, so each cell can
implement combinations like
  - one or two INV
  - one or two NOR2
  - INV and NOR2
  - one NOR3 or NOR4
I'm not sure about more complex logic, nor have I figured out the
idiom for storage (latch or flop)

For a given logic gate, you need to connect a current source to one or
both double transistors and connect a pullup resistor to the output
node.  Also need a pullup for the current sources (a connection which
I didn't label.)  As there are two current sources and three pullup
resistors, it's possible to make two independent logic gates.

The power supply rails are diffused into the bulk silicon and are not
visible.

It seems that the two cell designs are logically equivalent.

Hope this is useful
Ed