Date   : Fri, 20 May 1983 08:50:00 EDT
From   : WESTFALL.HENR@parc-maxc.arpa
Subject: P128k and 6509 cpu

Someone recently was looking for some info on the 6509 cpu. The 82-83
data book by MOS tech ( a commodore company) has this to say about the
chip.
 (Product preview)

o  1 megabyte addressing
o  3 state 16 bit address bus allowing dma and multiprocessor systems
sharing a common memory while the 4 bit extended address register allows
for up to 1 megabyte of data- storage
o  internal architecture is identical to the 6502 to provide software
compatiblilty

Features of the 6509
o  memory management
o  on board clock logic
o  addressable memory rage to 1 mbyte
o  single +5 supply
o  n channel, silicon gate, depletion load technology
o  8 bit parallel processing
o  56 instructions
o  decimal and binary instructions
o  13 addressing modes
o  true indexing capability
o  programmable stack pointer
o  variable length stack
o  interrupt capability
o  8 bit bi-directional data bus
o  Program accessable memory range of up to 65k bytes
o  Direct memory access capability
o  bus compatable with 6800
o  pipeline architecture
o  1 ,2 or 3 mhz operation
o  use with and type or speed memory

The info I have is just one page in the data book, however I did notice
a few things ( they include a pin out of the chip- but no pin
descriptions)

       40 pin package
       pins are as follows:
       ready, irq/, sync, nmi/, aec, Vdd, a0-a15, Vss, p0-p3,s.o., d0-d7,
r/w, o2 out, reset, o0 in

       the p0-p3 lines appear to be the high 4 bits on the address, making
this a bank select type machine.
The chip looks interesting, however they don't say if those 4 high bits
will tristate along with the 16 address bits

Rob Westfall
Xerox Corp
Henrietta, NY