Date   : Fri, 22 Mar 1985 09:39:00 PST
From   : CHERRY.ES@XEROX.ARPA
Subject: Re: Dynamic Memory

Do you really want to know?.... well Ok ...

1.  256K DRAMs are usually configured as 256K X 1 bit.  as such it will
require 8 chips to make a byte and 16 to make a work (if 2 bytes per
word).  

1a.  Don't for get the price of the circuit board, misc. logic, etc.

2.  DRAMs require refresh cycles while statics do not.  There are
usually 3-4 transistors to a DRAM cell and 6-7 transistors for a SRAM
cell.  As a result, for a given amount of die area, you can only get
about half as many static cells as you can dynamic cells.

3.  SRAMs can be built in bipolar, ECL, TTL, CMOS, MOS, and just about
anyother technology as they are basically a flip-flop.  These
technologies (bipolar: TTL, ECL, and to some extent CMOS) offer higher
performance due to their lower capacitances. 

DRAMs on the other hand are a capacitor which much be charged (write)
and recharged (refresh) or discharged (erase/clear) and the amount of
charge must be sensed without discharging the cell (read).  Since MOS
devices are typically capacitive devices (insulated gate), this is the
technology which is used most often for DRAMs.  Due to the higher
capacitances in MOS devices, they require longer times to access, read,
and write.  

Times of both SRAM/DRAM are measured in access time in nano-seconds (ns)

4.  Due to the nature of SRAMs, if they are built in CMOS, then, if
there are no clock signals peing provided to the chip, the power
consumption is almost 0.  CMOS basically is composed of both P-Well and
N-Well MOS devices and generally only one type is on at a time (per
cell).  With no clocks on the chip, the chip is not changing states and
all that is required is sufficient power to maintain the state of the
individual memory cells.  It is the changing of states which uses power
(current) as sufficient power must be provided to overcome intermal
loading of the various networks within the chip.

5.  The bus configuration (s-100, multibus, etc.) has nothing to do with
how a chip is refreshed.  Some chips offer "on-board" or "on-chip"
refresh.  Some RAMS are "dual-ported" (one port to the CPU, one port to
the system bus).  Some microprocessors (z80) provide the refresh pulse
and address while others do not.


I hope this helps answer your questions.  

Bob Cherry
Cherry.es@Xerox.Arpa
(213) 536-7654