Date   : Fri, 28 Nov 1986 02:16:32 GMT
From   : Jim Greenlee <jkg@gitpyr.gatech.edu>
Subject: Re: Interrupts on the N* Advantage

In article <1078@brl-adm.ARPA> rbloom@APG-1.ARPA (Robert Bloom AMSTE-TEI
3775) writes:
>     At the interrupt, the z80 jumps to the interrupt routine.  
>Where?  My z80 book says, "the z80 expects an [RST or CALL] 
>instruction to be placed on its data buss [by the interrupting 
>device]"  how it do dat?  Two people who I asked said "to where 
>you program it to" but I have no idea how to do that.

OK, here is my fuzzy recollection of how interrupts work on the Z80:

There are three interrupt modes on the Z80 - 0, 1, and 2. The mode is selected
by executing an IM instruction whose operand is the mode desired.

Mode 0 is the 8080-compatible mode. The Z80 expects the interrupting device
to put a value out on the data bus which indicates what location to jump to.
Their are 8 choices - 0H, 8H, 10H, 18H, 20H, 28H, 30H, and 38H. The processor
executes a CALL instruction to one of these locations, which contains either
an interrupt handler (if it can be handled with only 8 bytes of code) or a
JMP instruction to another location which contains the interrupt handler.

Mode 1 is the simplest mode. All maskable interrupt requests are vectored to
location 38H via a CALL instruction. This mode is equivalent to executing an
RST 7 in Mode 0.

Mode 2 is the most flexible mode, with full vectoring to any location you 
want. In this mode a priority is established among peripherals which can
generate an interrupt. This is done by daisy-chaining the peripherals through
the IEI/IEO pins. Whenever a device generates an interrupt, it pulls its
IEO output low. Also every device in the chain monitors its IEI pin. If this
pin goes low, then the device is disabled from producing interrupts, and the
device will again pull its IEO pin low. In this way, devices farther down the
chain are prevented from interrupting the processor while it is servicing a
higher priority interrupt.

Once this happens, the device puts an 8 bit vector on the data bus. The Z80
reads this vector, which must be programmed as part of the device's initial-
ization, and concatenates it with the contents of the I register. This register
is set to be the high order 8 bits of a 256 byte vector table. This table
can be located anywhere in memory - this is what your friends mean by "it's
wherever you put it". The 8 bit vector from the peripheral points to one of
the 256 locations in this table, which contains the start address of the inter-
rupt handler. You can have several of these tables in memory and switch back 
and forth simply be changing the contents of the I register.

If this is still confusing, e-mail me any specific questions you have and I'll
try to answer them. As I said, it's been a while since I did any Z80 stuff and
my memory is a little fuzzy, but I'll do my best.

                                              Jim Greenlee

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