Date : Tue, 09 Feb 1988 17:12:33 GMT
From : tektronix!zeus!dadla!donk@ucbvax.Berkeley.EDU (Donald C. Kirkpatrick;1236;92-716;LP=A;60iC)
Subject: Z280 Errata
In article <1635@mipos3.intel.com> dbraun@cadev4.UUCP (Doug Braun ~) writes:
>In article <8801301850.AA19041@newton.arpa> bridger%rcc@RAND-UNIX.ARPA
(Bridger Mitchell) writes:
>>My third-hand understanding is that the current z280 mask doesn't
>>correctly handle code (and data?) changes that occur in the
>>associative cache memory. Self-modifying code is therefore
>>unreliable, and possibly there are problems with data values also.
>
>I have heard:
>1: The above is a problem only in 8-bit bus mode. (I use 16-bit)
>2: The latest mask revision (due out any day now) has fixed this.
>
>Doug Braun Intel Corp CAD
> 408 496-5939
>
Here is the official bug sheet, as I received it from ZILOG:
===========
Subject: Z280 Errata Dated: 06/05/87 at 1522.
This document is a list of known bugs on the Z280 silicon,
Revision G.
1. POSSIBLE CACHE CORRUPTION.
This bug happens only when the Z280 is used in the Z80 bus
mode. It can be attributed to the fact that the Z280 is
designed as a 16-bit device with internal logic geared
towards the transfer of words instead of bytes.
In the Z80 bus mode with the cache enabled, a memory read of
word quantity data (not instructions) causes the cache to be
updated inadvertently. This happens only if the word data
address is even aligned. This is best explained in the
following example:
The stack pointer (xSP) is pointing to location 1004H. The
contents of external memory (not cache) locations 1004H and
1005H are "BB" and "CC" respectively. When a "POP HL"
instruction is executed, the problem will exhibit itself.
For correct operation, the following events should occur:
a. Memory Read Transaction with address "001004"
valid at time of address strobe (AS). When read
(RD) is asserted, the data bus should contain
"BB." Cache location "001004" should be updated to
"BB" and validated. Register L should now contain
"BB" as well.
b. Memory Read Transaction with address "001005"
valid at time of address strobe (AS). When read
(RD) is asserted, the data bus should contain
"CC." Cache location "001005" should be updated to
"CC" and validated. Register H should now contain
"CC" as well.
Due to the errata, the following takes place instead:
a. Memory Read Transaction with address "001004"
valid at time of address strobe (AS). When read
(RD) is asserted, the data bus contains "BB."
Cache location "001004" inadvertently gets updated
to "10" (contents of A15-A8) instead of "BB."
Cache location "001005" gets updated to "BB"
instead of "CC." Register L now contains "BB" as
well.
b. No second Memory Read Transaction takes place
externally due to the fact that the cache now has
"valid" data at location "001005" and supplies
that data to the instruction. Register H now
contains "BB" as well.
This anomaly can be negated through any of the
following methods:
a. Use Z-Bus mode instead of Z80.
b. Ensure that word data is odd-aligned. This will
force two read cycles to occur in order to fetch
the data.
c. Ensure that no code resides in the same 16-byte
memory space (0-F) that data resides in (A23-A4
cannot be the same).
d. Disable cache.
2. BURST MODE MEMORY TRANSACTIONS.
It has been discovered that the burst memory cycle does not
function as described when in the X2 and X4 bus clock modes.
It does function as specified in the X1 bus clock mode. What
happens is that the IE signal behaves as if it were a normal
memory access cycle.
This should not impact many applications because the burst
mode is used for high performance, and the highest
performance should be observed with the X1 bus clock mode.
=========== End of Errata ===========
Rev H silicon is in the characterization stage and will go to
production within the next 60 days. Beta test sites already
have silicon for evaluation.
Don Kirkpatrick
9 February 1988
End of INFO-CPM Digest
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